Yvon Trinquet

STORM a simulation tool for real-time multiprocessor scheduling evaluation

The increasing complexity of the hardware multiprocessor architectures as well as of the real-time applications they support makes very difficult even impossible to apply the theoretical real-time multiprocessor scheduling results currently available. Thus, so as to be able to evaluate and compare real-time multiprocessor scheduling strategies on their schedulability performance as well as energy efficiency, we have preferred a simulation approach and are developing an open and flexible multiprocessor scheduling simulation and evaluation platform called STORM. This paper presents the simulator on which STORM relies and that is able to simulate accurately the behaviour of those (hardware and software) elements that act upon the performances of such systems.

Trampoline An Open Source Implementation of the OSEK/VDX RTOS Specification

This paper introduces an OSEK/VDX operating system implementation. OSEK/VDX is an industry standard for real-time operating system used in the field of automotive embedded software. This implementation is proposed in the context of the open source software, which interest needs not to be demonstrated any more. The paper explains the main implementation choices as well as the technique proposed for the generation of a real-time application. This implementation is nowadays available for three targets: Infineon C167, Darwin/PowerPC and Linux/x86.

Adequacy between AUTOSAR OS specification and real-time scheduling theory

AUTOSAR (AUTOmotive Open System ARchitecture) consortium is a development partnership between the main actors of the automotive manufacturing industry. It aims at defining an open standardized software architecture, in order to face the future challenges in automotive development. One of the important challenge concerns the development of time-critical systems, e.g. brake-by-wire or steer-by-wire. In order to master the development of such systems, one must be able to understand and analyze their real-time behavior. Responses to this problem can be found in the real-time scheduling theory, especially schedulability analysis techniques. In this paper, we propose a review of a subset of the AUTOSAR Operating System specification from a schedulability analysis point-of-view.

An analysis of the AUTOSAR OS timing protection mechanism

The in-vehicle embedded system market is evolving toward a large improvement of the industrialization of the embedded software. One of the technical consequences of this evolution is the mandatory integration of protection mechanisms in the embedded operating system kernels to support the design of multi-suppliers multi-critical component-based embedded software. In this paper, we evaluate such a mechanism: the timing protection mechanism proposed in the AUTOSAR OS standard. This evaluation shows that the present version of the mechanism is not fully adapted to multi-critical systems because it does not handle soft/non real-time applications.

Implementing a semi-active replication strategy in CHORUS/ClassiX, a distributed real-time executive

The paper reports a practical implementation of a strategy to support semi-active replication of real-time software components (i.e. sets of tasks) running on the Chorus/ClassiX distributed operating system. The main property of the replication strategy developed in this paper is to solve the major difficulty of replica determinism. The semi-active replication scheme consists of a leader software component and identical follower replicas. Only the leader component sends out application messages as well as notifications indicating the order the messages have been consumed and produced. Dynamic non-deterministic scheduling of tasks within the different replicas may cause the follower tasks to lag in their execution regarding the leader ones.

Instruction set simulator generation using HARMLESS, a new hardware architecture description language

Instruction set simulators are commonly used in embedded system development processes for early functional validation of code and exploration of new instruction set design. Such a simulator can be either hand-written or generated automatically, based on a Hardware Architecture Description Language. Automatically generated simulators are more maintainable and are faster to develop, but they also generally suffer from low performances in simulation speed and a lack of expressivity in the description. This paper introduces HARMLESS, a new language to automatically generate instruction set simulators. It differs from other languages in many ways: it resolves most expressivity issues and naturally offers a flexible description by explicitly splitting the syntax (mnemonic), format (binary code) and behavior descriptions. Thus, it allows an incremental description, starting for example by the disassembler (requiring format and syntax descriptions). When the first two descriptions are validated, the behavior description is added to obtain the simulator. Some results are also presented on the simulator build process, especially on the decoder generation. An instruction cache is also introduced to speed up simulation in the same order of magnitude as hand-written simulators. Some experimental results are eventually presented.

IMPLICIT STATE-SPACE REPRESENTATION : A UNIFYING FRAMEWORK FOR FWL IMPLEMENTATION OF LTI SYSTEMS

Abstract Practically, some intermediary realizations are used in order to simulate, numerically, dynamic systems. One of the most popular is the state-space realization. It reveals to be very useful to study the impact of Finite Word Length implementation, especially in the case of embedded controller. Numerous works concerned the design of the “best” realization concerning parameterisation, numerical noise minimisation or saving computation. This paper points out however that a standard state-space realization is too basic to take into account some interesting realizations. On the contrary, it highlights that implicit state-space realizations allows a more direct link with the macroscopic computations to be performed. It is necessary to describe some popular algorithms simulating LTI systems. Moreover, such a representation has the important property to unify different ways of research considering differently the possibilities offered by using the shift, δ or γ operators.

An ADL Centric Approach for the Formal Design of Real-Time Systems

This paper presents the REACT project, dedicated to real-time system design. REACT aims at combining into an architectural design process some formal modelling and verification techniques and providing those corresponding tools. It emphasizes on the ADL of REACT (CLARA), and the validation of functional architectures using formal techniques.

A Data Flow Monitoring Service Based on Runtime Verification for AUTOSAR

This paper presents the design and implementation of an error detection service for multicore real-time in-vehicle embedded systems. The service aims at monitoring the data flows in a graph of communicating real-time tasks and detecting violation of the expected communication patterns. The service is not based on any specific system model. The monitors are automatically generated from formal models of the monitored system and the expected communication patterns. To minimize the time overhead of the service, the monitors are embedded in the RTOS kernel. The implementation targets an AUTOSAR-like platform based on the open-source RTOS Trampoline. Measures made on an ARM7 MCU show that the time and memory overheads are compatible with the stringent constraints of the application domain.

Harmless, a hardware architecture description language dedicated to real-time embedded system simulation

Validation and verification of embedded systems through simulation can be conducted at many levels, from the simulation of a high-level application model to the simulation of the actual binary code using an accurate model of the processor. However, for real-time applications, the simulated execution time must be as close as possible to the execution time on the actual platform and in this case the latter gives the closest results. The main drawback of the simulation of applications software using an accurate model of the processor resides in the development of a handwritten simulator which is a difficult and tedious task. This paper presents Harmless, a hardware architecture description language (ADL) that mainly targets real-time embedded systems. Harmless is dedicated to the generation of simulators for hardware platforms to develop and test real-time embedded applications. Compared to existing ADLs, Harmless (1) offers a more flexible description of the instruction set architecture (ISA) (2) allows to describe the microarchitecture independently of the ISA to ease its reuse and (3) compares favorably to simulators generated by the existing ADLs toolsets.