Z. A. K. Durrani

Room temperature nanocrystalline silicon single-electron transistors

Single-electron transistors operating at room temperature have been fabricated in 20-nm-thick nanocrystalline silicon thin films. These films contain crystalline silicon grains 4 – 8 nm in size, embedded in an amorphous silicon matrix. Our single-electron transistor consists of a side-gated 20 nm×20 nm point contact between source and drain electrodes. By selectively oxidizing the grain boundaries using a low-temperature oxidation and high-temperature argon annealing process, we are able to engineer tunnel barriers and increase the potential energy of these barriers. This forms a “natural” system of tunnel barriers consisting of silicon oxide tissues that encapsulate sub-10 nm size grains, which are small enough to observe room-temperature single-electron charging effects. The device characteristics are dominated by the grains at the point contact. The material growth and device fabrication process are compatible with silicon technology, raising the possibility of large-scale integrated nanoelectronic sys...

Charge injection and trapping in silicon nanocrystals

The temperature dependence of the conduction mechanism in thin films of ∼8nm diameter silicon nanocrystals is investigated using Al∕Sinanocrystal∕p‐Si∕Al diodes. A film thickness of 300 nm is used. From 300 to 200 K, space charge limited current, in the presence of an exponential distribution of trapping states, dominates the conduction mechanism. Using this model, a trap density Nt=2.3×1017cm−3 and a characteristic trap temperature Tt=1670K can be extracted. The trap density is within an order of magnitude of the nanocrystal number density, suggesting that most nanocrystals trap single or a few carriers at most.

A MEMORY CELL WITH SINGLE-ELECTRON AND METAL-OXIDE-SEMICONDUCTOR TRANSISTOR INTEGRATION

A single-electron transistor memory cell with metal-oxide-semiconductor field-effect transistor sensing has been fabricated in silicon-on-insulator material. The single-electron transistor, coupled to a memory node, is defined in the upper silicon layer. The memory node forms the gate of a metal-oxide-semiconductor field-effect transistor with its channel in the substrate silicon. At 4.2 K, there are two different states of the memory-node voltage, separated by the single-electron transistor Coulomb gap. These states are sensed at high-current output levels by the metal-oxide-semiconductor transistor. The metal-oxide-semiconductor transistor current also shows evidence of gate-dependent conductance oscillations in the coupled single-electron transistor.

Growth, structure, and transport properties of thin (>10 nm) n-type microcrystalline silicon prepared on silicon oxide and its application to single-electron transistor

Microcrystalline silicon (μc-Si:H) thin films were prepared at 300 °C on glass. Their structure and transport properties were studied in a wide range of film thickness ranging from 10 nm to 1 μm. The crystal fraction increases monotonously from ∼64% to ∼100% as film thickness increases. Electron mobility first increases with increasing film thickness at thicknesses smaller than 50 nm but saturates at larger thickness. This mobility behavior is explained by percolation transport through crystalline grains. These results are different from those obtained with preferentially oriented polycrystalline silicon films. It is related to the difference in the microstructure evolution in which subsequent film growth is influenced by the growth surface structure. A single-electron transistor fabricated in 30-nm-thick μc-Si:H exhibits Coulomb blockade effects at 4.2 K. This result indicates that amorphous phases which exist between crystalline grains behave as tunnel barrier for electrons.

Hopping conduction in size-controlled Si nanocrystals

We investigate the temperature dependence of conduction in size-controlled silicon nanocrystals. The nanocrystals are ∼8nm in diameter, covered by ∼1.5nm thick SiO2 shells. In 300nm thick films for temperatures T from 30to200K, the conductivity σ follows a ln(σ) vs 1∕T1∕2 dependence. This may be associated with either percolation-hopping conductance or Efros-Shklovskii variable range hopping. Assuming hopping sites only on the nanocrystals, the data agree well with the percolation model.

Single-electron effects in heavily doped polycrystalline silicon nanowires

We have observed single-electron charging effects in heavily doped polycrystalline silicon nanowires at 4.2 K. Wires of approximately 20 nm by 30 nm active cross section were defined by electron-beam lithography and thermal oxidation in standard polycrystalline silicon material. We have measured a Coulomb staircase and periodic current oscillations with gate bias, attributed to localized carrier confinement resulting from a statistical variation in the intergrain tunnel barriers. A sharp change in the current oscillation period is seen and we speculate that it is due to electrostatic screening of the gate bias by grain boundary defect states.

Single-electron devices and circuits in silicon

Introduction Physics of Single-Electron Charging Effects Silicon Single-Electron Transistors Quantum Dots in Silicon Silicon Single-Electron Memory Silicon Single-Electron Transfer Devices Silicon Single-Electron Logic Devices.

Coulomb blockade memory using integrated single-electron transistor/metal-oxide-semiconductor transistor gain cells

A 3/spl times/3-bit Coulomb blockade memory cell array has been fabricated in silicon-on-insulator (SOI) material. In each cell, the Coulomb blockade effect in a single-electron transistor is used to define two charge states. The charge is stored on a memory node of area 1 /spl mu/m/spl times/1 /spl mu/m or 1 /spl mu/m/spl times/70 nm and is sensed with gain by a metal-oxide-semiconductor transistor. The write/read operation for a selected cell within the array is demonstrated. The measured states are separated by /spl sim/1000 electrons for the 1 /spl mu/m/spl times/1 /spl mu/m memory node cell and by 60 electrons for the 1 /spl mu/m/spl times/70 nm memory node cell. Single-electron transistor controlled operation persists up to a temperature of 65 K.

Seebeck coefficient in silicon nanowire arrays

We measure the Seebeck coefficient S in large arrays of lightly doped n-Si nanowires (SiNWs). Our samples consist of ∼107 NWs in parallel, forming a “bulk” nano-structured material. We find that the phonon drag component of S, a manifestation of electron-phonon scattering in the sample, is heavily suppressed due to surface scattering, and that there is a “universal” temperature dependence for S. Furthermore, at room temperature, S is enhanced in the arrays by up to ∼3 times in comparison to bulk Si.

Room temperature single electron charging in single silicon nanochains

Single-electron charging effects are observed at room temperature in single Si nanochains. The nanochains, grown by thermal evaporation of SiO solid sources, consist of a series of Si nanocrystals ∼10nm in diameter, separated by SiO2 regions. Multiple step Coulomb staircase current-voltage characteristics are observed at 300K in devices using single, selected, nanochains. The characteristics are investigated using a model where the nanochain forms a multiple tunnel junction. The single-electron charging energy for a nanocrystal within the multiple-tunnel junction is EC=e2∕2Ceff∼0.32eV, ∼12kBT at 300K.