Z.W. Zhong

Impact life prediction modeling of TFBGA packages under board level drop test

Abstract Reliability performance of IC packages during drop impact is critical, especially for handheld electronic products. Currently, there is no model that provides good correlation with experimental measurements of acceleration and impact life. In this paper, detailed drop tests and simulations are performed on TFBGA (thin-profile fine-pitch BGA) and VFBGA (very-thin-profile fine-pitch BGA) packages at board level using testing procedures developed in-house. The packages are susceptible to solder joint failures, induced by a combination of PCB bending and mechanical shock during impact. The critical solder ball is observed to occur at the outermost corner solder joint, and fails along the solder and PCB pad interface. Various testing parameters are studied experimentally and analytically, to understand the effects of drop height, drop orientation, number of PCB mounting screws to fixture, position of component on board, PCB bending, solder material, etc. Drop height, felt thickness, and contact conditions are used to fine-tune the shape and level of shock pulse required. Board level drop test can be better controlled, compared with system or product level test such as impact of mobile phone, which sometimes has rather unpredictable results due to higher complexity and variations in drop orientation. At the same time, dynamic simulation is performed to compare with experimental results. The model established has close values of peak acceleration and impact duration as measured in actual drop test. The failure mode and critical solder ball location predicted by modeling correlate well with testing. For the first time, an accurate life prediction model is proposed for board level drop test to estimate the number of drops to failure for a package. For the correlation cases studied, the maximum normal peeling stresses of critical solder joints correlate well with the mean impact lives measured during the drop test. The uncertainty of impact life prediction is within ±4 drops, for a typical test of 50 drops. With this new model, a failure-free state can be determined, and drop test performance of new package design can be quantified, and further enhanced through modeling. This quantitative approach is different from traditional qualitative modeling, as it provides both accurate relative and absolute impact life prediction. The relative performance of package may be different under board level drop test and thermal cycling test. Different design guidelines should be considered, depending on application and area of concern.

Advanced experimental and simulation techniques for analysis of dynamic responses during drop impact

Board level solder joint reliability performance during drop test is a critical concern to semiconductor and electronic product manufacturers. A new JEDEC standard for board level drop test of handheld electronic products was just released to specify the drop test procedure and conditions. However, there is no detailed information stated on dynamic responses of printed circuit board (PCB) and solder joints which are closely related to stress and strain of solder joints that affect the solder joint reliability, nor there is any simulation technique which provides good correlation with experimental measurements of dynamic responses of PCB and the resulting solder joint reliability during the entire drop impact process. In this paper, comprehensive dynamic responses of PCB and solder joints, e.g., acceleration, strains, and resistance, are measured and analyzed with a multichannel real-time electrical monitoring system, and simulated with a novel input acceleration (Input-G) method. The solder joint failure process, i.e. crack initiation, propagation, and opening, is well understood from the behavior of dynamic resistance. It is found experimentally and numerically that the mechanical shock causes multiple PCB bending or vibration which induces the solder joint fatigue failure. It is proven that the peeling stress of the critical solder joint is the dominant failure indicator by simulation, which correlates well with the observations and assumptions by experiment. Coincidence of cyclic change among dynamic resistance of solder joints dynamic strains of PCB, and the peeling stress of the critical solder joints indicates that the solder joint crack opens and closes when PCB bends down and up, and the critical solder joint failure is induced by cyclic peeling stress. The failure mode and location of critical solder balls predicted by modeling correlate well with experimental observation by cross-section and dye penetration test.

Board level drop test and simulation of TFBGA packages for telecommunication applications

Reliabilit!- perfonnance of IC packages during drop impact is critical, especially for handheld electronic products. Currently. thcrc is no detailed test standard in the industry to advise on the procedures for board level dmp test. nor there is any model Ilia1 providcs good correlation with experimental ineasiircinents of acceleration and impact life. In this paper; detailed drop tests and simulations are pcrfonned on TFBGA (Thin-profile Fine-pitch BGA) and VFBGA (Vey-thinprofile Fine-pitch BGA) packages at board level using testing procediires developed in-house. The packages are susceptible to solder joint failures, induced by a combination of PCB bending and iueclwnical shock during impact. The critical solder ball is obsewed to occur at the outennost comer solder .joint_ and fails along the solder and PCB pad interface. Various testing parameters are studied experimentally and analytically. to understand the effects of drop heightl drop oricntation, number of PCB mounting screws to fixture. position of component on board: PCB bending: solder material, and etc. Drop height, fclt thickness, and contact conditions are used to fine-tune the shape aud level of shock pulse required. Board level drop test can be better controlled. compared with system or product level test such as impact of mobile phone. which sometimes has rather unpredictable results due to higher complexity and variations in drop orientation. At tlie same time, dynamic simulation is perfonncd to compare with esperiniental results. The model established has close values of peak acceleration and impact duration as measured in actual drop test. The failure mode and critical solder ball location predicted by modeling correlate well with testing. For the first time, an accurate life prediction model is proposed for board level drop test to estiinatc the number of drops to failure for a package. For the correlation cases studied. the nminmm nonual peeling stresses of critical solder joints correlate well with the mean impact lives measured during the drop test. The uncertainty of impact life prediction is within M drops, for a typical test of 50 drops. With this new model, a failure-free state can be detennined, and drop test performance of new package design can be quantified. and fuliher enhanced through modeling. This quantitative approach is different from traditional qualitative modeling. as it provides both accurate relative and absolute impact life prediction. The relative performance of package may be different under board level drop test ,and thennal cycling test. Different design guidelines should be considered, depcnding on application and area of concern

Design concept evaluation in product development using rough sets and grey relation analysis

Design concept evaluation plays a critical role in the early phases of product development as it has significant impact on the downstream development processes as well as on the success of the product developed. Essentially, design concept evaluation is a complex multi-criteria decision-making process involving large amount of data and expert knowledge which are usually imprecise and subjective. Aiming to improve the effectiveness and objectivity of the design concept evaluation process, this paper proposes a novel method based on grey relation analysis and rough set theory. By integrating the strength of rough sets in handling vagueness and the merit of grey relation analysis in modeling multi-criteria decision-making, a rough number enabled grey relation analysis (called rough-grey analysis) is proposed to evaluate design concepts. The result of an example shows that the proposed rough-grey analysis has provided a novel alternative to perform design concept evaluation, in which the vague design information and expert knowledge can be modeled and analyzed more effectively and objectively.

Integrated vapor pressure, hygroswelling, and thermo-mechanical stress modeling of QFN package during reflow with interfacial fracture mechanics analysis

Abstract In this paper, a comprehensive and integrated package stress model is established for quad flat non-lead package with detailed considerations of effects of moisture diffusion, heat transfer, thermo-mechanical stress, hygro-mechanical stress and vapor pressure induced during reflow. The critical plastic materials, i.e., moldcompound and die attach are characterized for hygroswelling and moisture properties, which are not easily available from material suppliers. The moisture absorption during preconditioning at JEDEC Level 1, and moisture desorption at various high temperatures are characterized. The moisture diffusivity is a few orders higher at reflow temperature than moisture preconditioning temperature. Due to coefficient of moisture expansion mismatch among various materials, hygro-mechanical stress is induced. The concept is analogous to coefficient of thermal expansion mismatch which results in thermo-mechanical stress. Thermal diffusivity is much faster than the moisture diffusivity. During reflow, the internal package reaches uniform temperature within a few seconds. The vapor pressure can be calculated based on the local moisture concentration after preconditioning. Results show that the vapor pressure saturates much faster than the moisture diffusion, and a near uniform vapor pressure is reached in the package. The vapor pressure introduces additional strain of the same order as the thermal strain and hygrostrain to the package. Subsequently, the interfacial fracture mechanics model is applied to study the effect of crack length on die/mold compound and die/die attach delamination.

Modal analysis and dynamic responses of board level drop test

Board level solder joint reliability during drop test is a great concern to semiconductor and electronic product manufacturers. In this paper, comprehensive dynamic responses of printed circuit boards (PCBs) and solder joints, e.g., acceleration, strains, and resistance, are measured and analyzed in detail with a multi-channel real-time electrical monitoring system. Control and monitoring of dynamic responses are very important to ensure consistent test results and understand the mechanical behaviors, as they are closely related to solder joint failure mechanisms. The effects of test variables, such as drop height, number of PCB mounting screws, tightness of screws, and number of felt layers, are studied by comparing and analyzing the dynamic responses.

A dominance-based rough set approach to Kansei Engineering in product development

Keen competitions in the global market have led product development to a more knowledge-intensive activity than ever, which requires not only tremendous expert knowledge but also effective analysis of design information. Kansei Engineering as a customer-oriented methodology for product development, often has to analyse imprecise design information inherent with nonlinearity and uncertainty. This paper proposes a systematic approach to Kansei Engineering based on the dominance-based rough set theory. Two novel concepts known as category score and partition quality have been developed and incorporated into the proposed approach. The new approach proposed is able to identify and analyse two types of inconsistencies caused by indiscernibility relations and dominance principles respectively. The result of an illustrative case study shows that the proposed approach can effectively extract Kansei knowledge from imprecise design information, and it can be easily integrated into an expert system for customer-oriented product development.

Novel numerical and experimental analysis of dynamic responses under board level drop test

Board level solder joint reliability during drop test is a great concern to semiconductor and electronic product manufacturers. A new JEDEC standard for board level drop test of handheld electronic products was just released to specify the drop test procedure and conditions. In this paper, comprehensive dynamic responses of PCB and solder joints, e.g., acceleration, strains, and resistance, are measured and analyzed in detail with a multi-channel real-time electrical monitoring system. It is found experimentally and numerically that the mechanical shock causes multiple PCB bending or vibration which induces the solder joint fatigue failure. A novel input acceleration (input-G) method is developed to simulate the exact drop test process using ANSYS-LSDYNA software. The model can be applied to simulate the overall impact responses including PCB cyclic bending, which are very critical for understanding of board level drop test.

Board level solder joint reliability modeling and testing of TFBGA packages for telecommunication applications

Abstract For thin-profile fine-pitch BGA (TFBGA) packages, board level solder joint reliability during the thermal cycling test is a critical issue. In this paper, both global and local parametric 3D FEA fatigue models are established for TFBGA on board with considerations of detailed pad design, realistic shape of solder joint, and nonlinear material properties. They have the capability to predict the fatigue life of solder joint during the thermal cycling test within ±13% error. The fatigue model applied is based on a modified Darveaux’s approach with nonlinear viscoplastic analysis of solder joints. A solder joint damage model is used to establish a connection between the strain energy density (SED) per cycle obtained from the FEA model and the actual characteristic life during the thermal cycling test. For the test vehicles studied, the maximum SED is observed at the top corner of outermost diagonal solder ball. The modeling predicted fatigue life is first correlated to the thermal cycling test results using modified correlation constants, curve-fitted from in-house BGA thermal cycling test data. Subsequently, design analysis is performed to study the effects of 14 key package dimensions, material properties, and thermal cycling test condition. In general, smaller die size, higher solder ball standoff, smaller maximum solder ball diameter, bigger solder mask opening, thinner board, higher mold compound CTE, smaller thermal cycling temperature range, and depopulated array type of ball layout pattern contribute to longer fatigue life.

Overview of wire bonding using copper wire or insulated wire

Wire bonding using copper or insulated wire leads to many advantages and new challenges. Research is intensively performed worldwide, leading to many new findings and solutions. This article reviews recent advances in wire bonding using copper wire or insulated wire for advanced microelectronics packaging. Journal articles, conference articles and patents published or issued recently are reviewed. The benefits and problems/challenges related to wire bonding using copper wire or insulated wire such as wire open and short tail defects, poor bondability for stitch/wedge bonds, oxidation of Cu wire, and stiff wire on weak support structures, are briefly analyzed. A number of solutions to the problems and recent findings/developments related to wire bonding using copper wire or insulated wire are discussed. With the references provided, readers may explore more deeply by reading the original articles and patent documents.