Zahava Koren

WDM passive star-protocols and performance analysis

A wavelength division multiplexing (WDM) transmissive star network is investigated, in which each node has one tunable transmitter with limited tuning capability and multiple fixed receivers. Two synchronous channel access protocols requiring no pretransmission penalty are considered: random access and fixed transmission scheduling. An efficient approximate analysis with drastically reduced computational complexity is presented. In spite of the reduced complexity, the presented approach produces very accurate results and can serve in producing the most cost-effective system design for given performance requirements.<<ETX>>

A unified negative-binomial distribution for yield analysis of defect-tolerant circuits

It has been recognized that the yield of fault-tolerant VLSI circuits depends on the size of the fault clusters. Consequently, models for yield analysis have been proposed for large-area clustering and small-area clustering, based on the two-parameter negative-binomial distribution. The addition of a new parameter, the block size, to the two existing parameters of the fault distribution is proposed. This parameter allows the unification of the existing models and, at the same time, adds a whole range of medium-size clustering models. Thus, the flexibility in choosing the appropriate yield model is increased. Methods for estimating the newly defined block size are presented and the approach is validated through simulation and empirical data. >

Designing interconnection buses in VLSI and WSI for maximum yield and minimum delay

Exact expressions for the yield of an interconnection bus as a function of its physical dimensions and the parameters and distribution of the possible open-circuit and short-circuit defects are derived. The effect of introducing redundancy into the bus is examined and the optimal layout of a given bus (with and without redundancy) is obtained. Any change in the layout of a bus may affect the propagation delay of the bus and, as a consequence, the performance of the VLSI chip. Hence, the delay of the designed bus in addition to its yield must be taken into account when determining the final layout of the bus. Both yield and delay are discussed through several numerical examples. >

Performance and design evaluation of WDM stars

In this paper, we provide a performance tool for evaluating the design of a WDM passive star. The design parameters which determine the system performance are the number of wavelengths in the system, the number of receivers per node, the wavelength allocation per receiver, the transmitter tunability range, and the node buffer size. An exact analysis becomes prohibitively complex for even moderately sized systems. We therefore present an efficient approximate analysis with drastically reduced computational complexity, incorporating all of the above design parameters, in addition to the channel access protocol and the nonhomogeneous traffic patterns of highbandwidth networks. The presented approach produces very accurate results, and can help in selecting the most cost-effective system design for given performance requirements

A self-correcting active pixel camera

Digital cameras on-a-chip are becoming more common and are expected to be used in many industrial and consumer products. With the size of the CMOS active pixel-array implemented in such chips increasing to 512/spl times/512 and beyond, the possibility of degradation in the reliability of the chip over time must be a factor in the chip design. In digital circuits, a commonly used technique for reliability or yield enhancement is the incorporation of redundancy (e.g., adding redundant rows and columns in large memory ICs). Very limited attempts have been directed towards fault-tolerance in analog circuits, mainly due to the very high level of irregularity in their design. Since active pixel arrays have a regular structure, they are amenable to reliability enhancement through a limited amount of added redundancy. The purpose of this paper is to investigate the advantages of incorporating some fault-tolerance methods, including redundancy, into the design of an active pixel sensor array.

Quantitative analysis of in-field defects in image sensor arrays

Growth of pixel density and sensor array size increases the likelihood of developing in-field pixel defects. An ongoing study on defect development in imagers has now provided us sufficient data to be able to quantify characteristics of defect growth. Preliminary investigations have shown that defects are distributed randomly and the closest distance between two defective pixels is approximately 79-340 pixels apart. Furthermore, from an observation of 98 cluster-free defects, the diameter of the defect is estimated to be less than 2.3% of a pixel size at 99% confidence level. The fact that no defect clusters were found in the study of various digital cameras allows us to conclude that defects are not likely to be related to material degradation or imperfect fabrication but are due to environmental stress such as radiation. Furthermore, as verified by a statistical study, the absence of defect clustering provides information on the size of defects and insight into the nature of the defect development.

The Hyeti defect tolerant microprocessor: a practical experiment and its cost-effectiveness analysis

This paper summarizes a practical experiment in designing a defect tolerant microprocessor and presents the underlying principles. Unlike memory integrated circuits, microprocessors have an irregular structure which complicates both the task of incorporating redundancy for defect tolerance in the design and the task of analyzing the resulting yield increase. The main goal of this paper is to present the detailed yield analysis of a defect tolerant microprocessor with an irregular structure which has been successfully fabricated. The approaches employed for achieving the goal of yield enhancement in the data path and the control part of the microprocessor are described first. Then, the yield enhancement due to the incorporated redundancy is analyzed. Finally, some practical and theoretical conclusions are drawn. >

Incorporating yield enhancement into the floorplanning process

The traditional goals of the floorplanning process for a new integrated circuit have been minimizing the total chip area and reducing the routing cost, i.e., the total length of the interconnecting wires. Recently, it has been shown that, for certain types of chips, the floorplan can affect the yield of the chip as well. Consequently, it becomes desirable to consider the expected yield, in addition to the cost of routing, when selecting a floorplan. The goal of this paper is to investigate the two seemingly unrelated, and often conflicting, objectives of yield enhancement and routing complexity minimization. We analyze the possible trade-offs between the two and then present a constructive algorithm for incorporating yield enhancement as a secondary objective into the floorplanning process, with the main objective still being the minimization of the overall routing costs.

Statistical Identification and Analysis of Defect Development in Digital Imagers

The lifetime of solid-state image sensors is limited by the appearance of defects, particularly hot-pixels, which we have previously shown to develop continuously over the sensor lifetime. Analysis based on spatial distribution and temporal growth of defects displayed no evidence of the defects being caused by material degradation. Instead, high radiation appears to accelerate defect development in image sensors. It is important to detect these faulty pixels prior to the use of image enhancement algorithms to avoid spreading the error to neighboring pixels. The date on which a defect has first developed can be extracted from past images. Previously, an automatic defect detection algorithm using Bayesian probability accumulation was introduced and tested. We performed extensive testing of this Bayes-based algorithm by detecting defects in image datasets obtained from four cameras. Our results have indicated that the Bayes detection scheme was able to identify all defects in these cameras with less than 3% difference from visual inspected result. In this paper, we introduce an alternative technique, the Maximum Likelihood detection algorithm, and evaluate its performance using Monte Carlo simulations based on three criterias: image exposure, defect parameters and pixel estimation. Preliminary results show that the Maximum likelihood detection algorithm is able to achieve higher accuracy than the Bayes detection algorithm, with 90% perfect detection in images captured at long exposures (>0.125s).

A self-correcting active pixel sensor using hardware and software correction

Active pixel sensor (APS) CMOS technology reduces the cost and power consumption of digital imaging applications. We present a highly reliable system for the production of high-quality images in harsh environments. The system is based on a fault-tolerant architecture that effectively combines hardware redundancy in the APS cells and software correction techniques.