Zbigniew Hajduk

Architecture of FPGA Embedded Multiprocessor Programmable Controller

This paper presents the design and implementation of a multiprocessor programmable controller in field-programmable gate array (FPGA). The novelty of the proposed solution is that it combines two approaches used so far in the domain of FPGA implementations of control algorithms, i.e., program based and hardware coded, and applies multiple processors in a single FPGA chip. The controller is programmed according to the IEC 61131-3 standard and runs control tasks in parallel. Performance tests of the prototype show that it is able to execute control programs significantly faster than industrial programmable logic controllers.

An FPGA embedded microcontroller

The paper presents the design of an 8-bit RISC microcontroller, which is mainly targeted for performing non-timing crucial functions inside FPGAs. The microcontroller is based on popular Microchip PIC16 microcontrollers family. The main feature of the microcontroller is that it is 4 times faster for regular instructions, and 8 times faster for instructions which modify program counter, than its Microchip archetype clocked at the same frequency. Three versions of the microcontroller instruction cycle structures have been considered and performance tests of the versions have also been carried out. The paper also describes two sample applications which illustrate the usefulness of the microcontroller and show that using the FPGA embedded microcontroller, realization of some functions can be simpler and faster than applying a typical FPGA design flow without the microcontroller. To facilitate frequent exchange of the microcontroller program memory content, specifically at the software developing stage, the downloader module has been proposed to use as well. The downloader allows to directly load the compilers HEX output file to the program memory using a generic serial interface.

Hardware Implementation of P1-TS Fuzzy Rule-Based Systems on FPGA

This paper presents an FPGA hardware implementation of a special case of the fuzzy rule-based system, called P1-TS. The novelty of this work is recursive hardware architecture. The recursive implementation of the rule-based system allows us to build a versatile digital circuit for which FPGA logic resources requirements are small and independent on the number of input variables. The number of inputs is only limited by the capacity of the memory that stores the consequents of the rules. In our implementation, increasing the number of variables by 1 approximately doubles calculation time of the hardware device. We use floating-point arithmetic which ensures a higher dynamic range and makes that there is no need to focus on normalizing variables values to fixed word length.

High accuracy FPGA activation function implementation for neural networks

This letter shortly presents an FPGA implementation method of the hyperbolic tangent and sigmoid activation functions for artificial neural networks. A kind of a direct implementation of the functions is proposed. The implementation results show that the obtained accuracy of the method is relatively high compared to other published solutions.

Hardware Implementation of Fuzzy Petri Nets with Lukasiewicz Norms for Modelling of Control Systems

In the paper an implementation of Fuzzy Petri Nets with Lukasiewicz norms is described based on FPGA integrated circuits. The proposed solution is used for modeling of control systems. The approach for the realization of fuzzy Petri net models is based on the synthesis method taking advantage of a fuzzy Petri net place module concept. The paper contains the description of a real-life control system, which is used to demonstrate new features of fuzzy Petri nets with Lukasiewicz norms. For the example control system, in order to analyze costs of implementation, a comparison is made between the fuzzy Petri net model with Lukasiewicz norms and the fuzzy Petri net model with triangular MIN/MAX norms.

FPGA-based communication interface for persons with motor neuron diseases

Abstract This paper focuses on the architecture and FPGA implementation aspects of a kind of assistive tool for disabled persons with motor neuron diseases, specifically with muscle atrophy. The tool, called a communication interface, allows such persons to communicate with other people by means of moving selected muscles, e.g., within the face. The application of MEMS accelerometers have been proposed as muscle movement sensors. Four different FPGA implementation methods of signal processing from MEMS sensors, i.e., manual HDL coding, usage of the Matlab HDL coder and Vivado HLS as well as embedded microcontroller exploitation, have been investigated. The communication interface can be used either as an input switch for, so called, virtual keyboards or as a stand-alone tool, which allows disabled persons to write a text by means of the Morse code.

Failures Prediction in the Cold Forging Process Using Machine Learning Methods

In this paper, single correct and three defective states for the cold headed fasteners production technological process are detected. Computational intelligence methods are used for this purpose: single decision tree, probabilistic neural network, support vector machine, multilayer perceptron, linear discriminant analysis and K–Means clustering. The predictor variables are taken in time and frequency domain. The row data sets consist of sampled signals of the real process collected in fasteners manufacturing company. The prediction ability determined by 10-fold cross validation is investigated by means of accuracy, sensitivity and specificity. The results show the superiority of probabilistic neural network and support vector machine classifiers. The average accuracy is over 98%.

Reconfigurable FPGA implementation of neural networks

Abstract This brief paper presents two implementations of feed-forward artificial neural networks in FPGAs. The implementations differ in the FPGA resources requirement and calculations speed. Both implementations exercise floating point arithmetic, apply very high accuracy activation function realization, and enable easy alteration of the neural networks structure without the need of a re-implementation of the entire FPGA project.