Zdravko Boos

A fully digital multimode polar transmitter employing 17b RF DAC in 3G mode

The constantly growing quest for global roaming with a fast mobile internet access has further increased demand for multiband 3G cell phones supporting also 2G/2.5G standards, in order to provide full coverage any time, any place. In order to substantially reduce cost and size of the multimode, multiband handsets, it is necessary to develop a transmitter architecture that enables use of a multimode, multiband power amplifier, a key prerequisite to substantially reduce the number of external components, pins count, and PCB area, while at the same time significantly lowering power consumption.

A 1.5-V 0.7–2.5-GHz CMOS Quadrature Demodulator for Multiband Direct-Conversion Receivers

An integrated quadrature demodulator with an on-chip frequency divider is reported. The mixer consists of a transconductance stage, a passive current switching stage, and an operational amplifier output stage. A complementary input architecture has been used to increase the transconductance for a given bias current. The circuit is inductorless and is capable of operating over a broad frequency range. The chip was implemented in a 0.13-mum CMOS technology. From 700 MHz to 2.5 GHz, the demodulator achieves 35 dB of conversion voltage gain with 250-kHz IF bandwidth, a double-sideband NF of 10 dB with 9-33 kHz 1/f-noise corner. The measured IIP3 is 4 dBm for a 0.1-MHz IF frequency and 10 dBm for a 1-MHz IF frequency. The total chip draws 20 to 24 mA from a single 1.5-V supply.

Digital Adaptive IIP2 Calibration Scheme for CMOS Downconversion Mixers

This paper presents a cancellation scheme of second order intermodulation distortion based on adaptive digital calibration of the RF downconversion mixer. The system utilizes a low-complexity LMS-based equalizer, which correlates differential mode distortion with common mode distortion to estimate optimum settings of the analog IP2 calibration circuit. A tunable IQ mixer prototype, fabricated in a 0.13 mum RF CMOS technology and operating under low voltage supply of 1.5 V, is presented. Experimental results confirm the feasibility of the proposed IP2 calibration method.

A 9 GHz dual-mode digitally controlled oscillator for GSM/UMTS transceivers in 65 nm CMOS

A 9 GHz fully digitally controlled oscillator implemented in 65 nm CMOS technology is presented. This is the first DCO implemented at 9 GHz which covers all transmitter (TX) and receiver (RX) bands of GSM/EDGE and UMTS except Band VII. It covers a coarse tuning range from 6.35 GHz to 9.15 GHz which is realized by binary weighted switchable capacitors. The phase noise performance meets the specifications of GSM/EDGE and UMTS with a low current consumption.

A 6ps resolution pulse shrinking Time-to-Digital Converter as phase detector in multi-mode transceiver

This paper presents a new phase detector in an all digital phase locked loop which converts the phase difference between one reference clock edge and one divided oscillator edge into a digital word. This digital word can be converted into a digital representation of the actual phase error which can be utilized in an all digital phase locked loop. 6 ps resolution for this time-to-digital converter (TDC) is realized in a standard 0.13 mum CMOS technology. Its full- scale-range (FSR) is 4500 ps.

Multi-stage Pulse Shrinking Time-to-Digital Converter for Time Interval Measurements

This paper presents a new structure of Pulse Shrinking Time-to-Digital Converter (TDC) with 20 ps resolution which is implemented in Infineon 0.13 mum CMOS technology. The new interpolating multi-stage TDC with feedback loop and high speed counter accelerates the digitization of the input time interval and is appropriate as Phase Detector for Phase Locked Loop application. The interpolated multi-stage structure efficiently saves the chip area and power consumption. Its Full-Scale-Range (FSR) is about 5000 ps and its differential linearity errors are less than 0.52 LSB.

A 1.5V 0.7-2.5GHz CMOS Quadrature Demodulator for Multi-Band Direct-Conversion Receivers

An integrated quadrature demodulator with an on-chip frequency divider is reported. The mixer consists of a transconductance stage, a passive current switching stage, and an operational amplifier output stage. A complementary input architecture has been used to increase the transconductance for a given bias current. The circuit is inductorless and is capable of operating over a broad frequency range. The chip was implemented in a 0.13-mum CMOS technology. From 700 MHz to 2.5 GHz, the demodulator achieves 35 dB of conversion voltage gain with 250-kHz IF bandwidth, a double-sideband NF of 10 dB with 9-33 kHz 1/f-noise corner. The measured IIP3 is 4 dBm for a 0.1-MHz IF frequency and 10 dBm for a 1-MHz IF frequency. The total chip draws 20 to 24 mA from a single 1.5-V supply.

A Multimode Receiver Front-end for Software Defined Radio

A flexible multimode receiver architecture for software defined radio systems with focus on GSM, WCDMA and CDMA systems has been designed in a 120 nm CMOS technology. The receiver consists of a wideband coilless common gate LNA2 with gain switches and a high linearity down-converter with current interface between mixer and baseband-filter. The LO signal of a 8 GHz VCO and divider with ratio 4 respectively 8 covers the whole receiver frequency range. The receiver consumes 32 mA at 1.5 V supply voltage

An inductorless high dynamic range 0.3 − 2.6 GHz receiver CMOS front-end

This paper presents a wideband receiver front-end implemented in 0.13 µm CMOS technology. The front-end consists of a low-noise amplifier (LNA), a quadrature mixer, and a frequency divider. Multi-gated transistors have been used to enable linearity tuning. The circuit employs no inductors and operates from 0.3 − 2.6 GHz with a tunable baseband bandwidth. The front-end achieves conversion voltage gain of 38 dB, 3.6 dB DSB NF, nominal −6.5 dBm IIP3 and +4 dBm when tuned in the high-gain mode. The chip consumes 35 mA from a 1.5 V supply

A 0.13μm 1.5V CMOS I/Q Downconverter with Digital Adaptive IIP2 Calibration

A low-voltage I/Q downconverter with digital adaptive IIP2 calibration is presented. The system maintains high linearity over time by continuously updating tuning codes in response to varying operating conditions. A prototype is fabricated in a 0.13μm RF CMOS process. At 2GHz LO, it draws 48mA from a 1.5V supply