Zhang Jun-an

A 2.5-GHz Direct Digital Frequency Synthesizer with spurious noise cancellation

A 2.5GHz Direct Digital Frequency Synthesizer (DDS) with spurious noise cancellation is presented. Seven auxiliary DDSs have been used as spur cancellers which can generate opposition signal to counteract the spurs in DDS’s output spectrum. Principle of spur cancellation and its implementation scheme is discussed. Key steps of spur cancellation procedure are also described. This DDS is implemented in a 0.18 μm CMOS technology, occupies 4.6mm # 4.2mm including bond pads. Measured performance is SFDR > 58dB for output signal frequencies up to 1GHz, more than 20 dB’s improvement is achieved comparing to its intrinsic SFDR performance.

A bandgap reference in 65nm CMOS

A bandgap reference circuit with voltage and current output is presented. Operational transconductance amplifier(OTA) have been used for a higher DC power supply rejection rate(PSRR) under small gate length of MOSfet. Both telescopic and folded OTA and low threshold voltage MOSfet have been used to ensure the circuit at suitable operation points under every PVT(process, source voltage and temperature) corner. Two opposite temperature coefficient resistors have been connected in series to obtain a temperature independent resistor for voltage references generation. This bandgap reference is implemented in a 65nm CMOS technology, occupies 0.75mm×0.67mm including bond pads, Measured results show that this circuit can operate at supply voltage from 1.1V to 1.3V, and the temperature coefficient of voltage output is 30.9ppm/oC with 61dB PSRR (DC, 25oC), and the temperature coefficient of current output is 51.6ppm/oC with 69dB PSRR (DC, 25 oC), among -55oC~125oC without any trimming or calibration.

Challenge of High Performance Bandgap Reference Design in Nanoscale CMOS Technology

To design a high performance bandgap reference circuit in nanoscale CMOS technology becomes a great challenge. Many negative effects of nanoscale CMOS technology in high performance bandgap reference design are discussed in this chapter. A bandgap reference circuit design with both voltage output and current output is presented also. In this design, low threshold voltage MOSfet have been utilized in this design to ensure the circuit at suitable DC operation points under extreme low temperature. Operational transconductance amplifier (OTA) has been used to achieve high DC power supply rejection rate (PSRR). Two opposite temperature coefficient resistors have been connected in series to obtain a one-order temperature independent resistor which also achieves a weak curvature compensation effect for reference voltage’s generation. This bandgap reference is implemented in a 65 nm CMOS technology, occupies 0.75 × 0. 67 mm including bond pads, Measured results show that this circuit can operate at supply voltage from 1.1 to 1.3 V, and the temperature coefficient of voltage output is 30 ppm/°C with 60 dB PSRR (DC, 30°C), and the temperature coefficient of current output is 52 ppm/°C with 70 dB PSRR (DC, 30°C), among −55°C to 125°C without any trimming or calibration.

A multi-chip synchronization system based on diversity technique

Abstract. A multi-chip synchronization system based on diversity technique is presented. As diversity technique in communication, at the master IC chip’s transmitter, two periodic synchronization signals (with a set delay time between them) have been sent as synchronization reference. At every IC chips’ receiver end, a searching method (by internal state machine) is used to obtain the proper receiving clock for the two synchronization signals’ reliable receiving, and the two received synchronization signals and an internal generated synchronization signal will be time aligned, only one of them is sent to reset the internal frequency divider. The two received synchronization signals are also monitored, and if any receiving error occurred, then the system will switch to use the other one or the internal one automatically. This multi-chip synchronization system can achieve a reliable multi-chip synchronization performance.

A 16-bit cascaded sigma-delta pipeline A/D converter

A low-noise cascaded multi-bit sigma-delta pipeline analog-to-digital converter (ADC) with a low over-sampling rate is presented. The architecture is composed of a 2-order 5-bit sigma-delta modulator and a cascaded 4-stage 12-bit pipelined ADC, and operates at a low 8X oversampling rate. The static and dynamic performances of the whole ADC can be improved by using dynamic element matching technique. The ADC operates at a 4 MHz clock rate and dissipates 300 mW at a 5 V/3 V analog/digital power supply. It is developed in a 0.35 μm CMOS process and achieves an SNR of 82 dB.