Zhangcheng Huang

Design of 800×2 low-noise readout circuit for near-infrared InGaAs focal plane array

InGaAs near-infrared (NIR) focal plane arrays (FPA) have important applications in space remote sensing. A design of 800×2 low-noise readout integrated circuit (T800 ROIC) with a pitch of 25 μm is presented for a dual-band monolithic InGaAs FPA. Mathematical analysis and transient noise simulations have been presented for predicting and lowering the noise in T800 ROIC. Thermal noise from input-stage amplifier which plays a dominant role in ROIC is reduced by increasing load capacitor under tradeoff and a low input offset voltage in the range of ±5 mV is obtained by optimizing transistors in the input-stage amplifier. T800 ROIC has been fabricated with 0.5-μm 5V mixed signal CMOS process and interfaced with InGaAs detector arrays. Test results show that ROIC noise is around 90 μV and input offset voltage shows a good correspondence with simulation results. 800×2 InGaAs FPA has a peak detectivity (D*) of about 1.1×1012 cmHz1/2/ W, with dynamic range of above 80dB.

A 1024×512 ROIC with 30μm pixel pitch and 250Hz high frame rate for shortwave infrared detector

In order to satisfy the requirements of short-wave infrared hyperspectral detection, we developed a 1024 x 512 ROIC with 30μm pixel pitch. CTIA with cascode amplifier was utilized as input stage and CDS was used for eliminating KTC noise and 1/f noise in CTIA. For this large chip with sizes up to 30mm x 20mm, it has been found that column circuit was a major bottleneck to achieve high frame frequency. A solution to solve this problem in this work is to pre-establish the signal of the column amplifier and then buffer odd and even column signals to the bus alternatively. In addition, parasitic capacitance of column-level bus was carefully lowered in layout design. The total readout rate reached 120 Mpixels/s with eight parallel output channels which allowed for a frame rate of 250 Hz.

Life test of the InGaAs focal plane arrays detector for space applications

The short-wavelength infrared (SWIR) InGaAs focal plane array (FPA) detector consists of infrared detector chip, readout integrated circuit (ROIC), and flip-chip bonding interconnection by Indium bump. In order to satisfy space application requirements for failure rates or Mean Time to Failure (MTTF), which can only be demonstrated with the large number of detectors manufactured, the single pixel in InGaAs FPAs was chosen as the research object in this paper. The constant-stress accelerated life tests were carried out at 70°C，80°C，90°C and100°C. The failed pixels increased gradually during more than 14000 hours at each elevated temperatures. From the random failure data the activation energy was estimated to be 0.46eV, and the average lifetime of a single pixel in InGaAs FPAs was estimated to be longer than 1E+7h at the practical operating temperature (5°C).

A low noise high readout speed 512×128 ROIC for shortwave InGaAs FPA

A low noise high readout speed 512×128 readout Integrated circuit (ROIC) based on capacitance trans-impedance amplifier (CTIA) is designed in this paper. The ROIC is flip-chip bonded with Indium bumps to InGaAs detectors which cutoff wavelength is 1.7μm, as a hybrid structure (InGaAs FPA). The ROIC with 30μm pixel pitch and 50fF integrated capacitance, is fabricated in 0.5μm DPTM CMOS process. The results show that output noise is about 3.0E-4V which equivalent readout noise is 95e-, output voltage swing is better than 2.5V; the dynamic range of InGaAs FPA reaches 69.7dB@2ms, and the power dissipation is about 175mw. The peak detectivity of InGaAs FPA reaches 2E12cmHz1/2w-1 at 300K without TEC cooling.

A low noise low power 512×256 ROIC for extended wavelength InGaAs FPA

A low noise low power 512×256 readout integrated circuit (ROIC) based on Capacitance Trans-impedance Amplifier (CTIA) was designed in this paper. The ROIC with 30μm pixel-pitch and 70 fF integrated capacitance as normal structure and test structure capacitance from 5 to 60 fF, was fabricated in 0.5μm DPTM CMOS process. The results showed that output voltage was larger than 2.0V and power consumption was about 150mW, output ROIC noise was about 3.6E-4V which equivalent noise was 160e-, and the test structure noise was from 20e- to 140 e-. Compared the readout noises in Integration Then Readout (ITR) mode and Integration While Readout (IWR) mode, it indicated that in IWR mode, readout noise comes mainly from both integration capacitance and sampling capacitance, while in ITR mode, readout noise comes mostly from sampling capacitance. Finally the ROIC was flip-chip bonded with Indium bumps to extended wavelength InGaAs detectors with cutoff wavelength 2.5μm at 200K. The peak detectivity exceeded 5E11cmHz1/2/w with 70nA/cm2 dark current density at 200K.

Analysis and simulation of a new kind of noise at the input stage of infrared focal plane array

Noise is a primary characteristic of an infrared focal plane array (FPA) that contributes to detection performance at low light level. In a capacitive-feedback trans-impedance amplifier (CTIA)-based readout integrated circuit (ROIC), reset noise can be removed by correlated double sampling (CDS). There is an exotic experimental phenomenon that FPA noise will increase greatly if the first sampling time of CDS is less than a threshold value. A noise model at FPA interface is presented in this paper which explains that this new kind of noise originates from incompletely settling of CTIA preamplifier. As this noise is performed in time domains, we use transient noise simulation technique to describe the dependence of this noise on detector pixel capacitance, integration capacitor, and some other design parameters. Based on the theoretical model analysis and simulation results, effective design method is obtained to reduce this kind of noise.

Study on 512×128 pixels InGaAs near infrared focal plane arrays

It is well known that In0.53Ga0.47As epitaxial material is lattice-matched to InP substrate corresponding to the wavelength from 0.9μm to 1.7μm, which results to high quality material and good device characteristics at room temperature. In order to develop the near infrared multi-spectral imaging, 512×128 pixels InGaAs Near Infrared Focal Plane Arrays (FPAs) were studied. The n-InP/i-InGaAs/n-InP double hereto-structure epitaxial material was grown by MBE. The 512×128 back-illuminated planar InGaAs detector arrays were fabricated, including the improvement of passivation film, by grooving the diffusion masking layer, the P type electrode layer, In bump condition and so on. The photo-sensitive region has the diffusion area of 23×23μm2 and pixel pitch of 30×30μm2 . The 512×128 detector arrays were individually hybridized on readout integrated circuit(ROIC) by Indium bump based on flip-chip process to make focal plane arrays (FPAs). The ROIC is based on a capacitive trans-impedance amplifier with correlated double sampling and integrated while readout (IWR) mode with high readout velocity of every pixel resulting in low readout noise and high frame frequency. The average peak detectivity and the response non-uniformity of the FPAs are 1.63×1012 cmHz1/2/W and 5.9%, respectively. The power dissipation and frame frequency of the FPAs are about 180mW and 400Hz, respectively.

Performance of near-infrared InGaAs focal plane array with different series resistances to p-InP layer

A planar-type InGaAs linear detector was designed and fabricated based on n-i-n+ type InP/In0.53Ga0.47As/InP epitaxial materials. The major process of the detector contains planar diffusion, surface passivation, metal contact and annealing. The I-V curves and the relative spectral response were measured at room temperature. The relative spectral response is in the range of 0.9 μm to 1.68 μm. The R0A of the detector is about 2×106 Ω•cm2 and the dark current density is 5~10nA/cm2 at -10mV bias voltage. The linear detectors were wire-bonded with readout integrated circuits (ROIC) to form focal plane array (FPA). The input stage of the ROIC is based on capacitive-feedback transimpedance amplifier (CTIA) with a capacitor (Cint) to be 0.1pF. However, the FPA signals are oscillating especially when close to the saturation. The ohmic contact on p-InP region plays an important role in the performance of detectors and FPAs. In this case, the series resistance to p-InP layer of each pixel is up to 1×106Ω. The FPAs were simulated in case of InGaAs detectors with different series resistances. According to the simulation results, the bandwidth of CTIA is lowering along with Rs increasing, and the signals of the FPAs oscillate when the series resistances are beyond 4×104Ω. The reason for the unstable oscillation of FPA is due to the series resistance of the detector which is too high enough. Then, the annealing process of the detectors was improved and the series resistances were lower than 1×104Ω. The optimized InGaAs linear detectors were wire-bonded with the same ROIC. The oscillation of the signals disappears and the FPA shows good stability.

Analysis of low-offset CTIA amplifier for small-size-pixel infrared focal plane array

The design of input stage amplifier becomes more and more difficult as the expansion of format arrays and reduction of pixel size. A design method of low-offset amplifier based on 0.18-μm process used in small-size pixel is analyzed in order to decrease the dark signal of extended wavelength InGaAs infrared focal plane arrays (IRFPA). Based on an example of a cascode operational amplifier (op-amp), the relationship between input offset voltage and size of each transistor is discussed through theoretical analysis and Monte Carlo simulation. The results indicate that input transistors and load transistors have great influence on the input offset voltage while common-gate transistors are negligible. Furthermore, the offset voltage begins to increase slightly when the width and length of transistors decrease along with the diminution of pixel size, and raises rapidly when the size is smaller than a proximate threshold value. The offset voltage of preamplifiers with differential architecture and single-shared architecture in small pitch pixel are studied. After optimization under same conditions, simulation results show that single-shared architecture has smaller offset voltage than differential architecture.

A 20MHz 15μm pitch 128×128 CTIA ROIC for InGaAs focal plane array

A 128×128 matrix readout integrated circuit (ROIC) for 15×15 μm2 InGaAs focal plane array (FPA) is reported in this paper. Capacitive-feedback Trans-Impedance Amplifier (CTIA) and correlated double sampling (CDS) are both involved in ROIC pixel which dissipates 90nW and has a full-well-capacity (FWC) of about 78,000 e-. Noises of ROIC pixel are analyzed and distribution method of capacitors in pixel is discussed in order to obtain low-noise performance. In column buffer circuit, a new pre-charging technique is developed to realize readout rate of 20 MHz with low power consumption. The ROIC is fabricated with 0.18-μm 3.3 V mixed signal CMOS process. Test results show that the ROIC has an equivalent input noise of about 181e- and can achieve a readout rate of 20 MHz.