Zhengyi Liu

Formal Verification of Controller Synthesis Based on Incompletely Specified Finite State Machine Model

The paper presents an inclusion relation which is used to verify the process of controller synthesis based on incompletely specified finite state machine model. State transition graph is adopted to describe the behavior of controller. State transition graph STG_org was abstract behavior description of controller synthesis generated before synthesized and state transition graph STGext was reversely extracted from structure realization of controller synthesis. If STG_org contains STGext then corresponding process of controller synthesis was correct. The paper gives a formal verification algorithm of controller synthesis with time complexity O(A₁ldrA₂ldrt₂ (m, n) + B₁ldrB₂ldrt₁ (n)) .In order to further improve time complexity of algorithm, a verifying algorithm with synthetic information guidance was proposed. The algorithm is proved efficient in theory for its time complexity is decreased to O(Cldr(B₁ldrt₁(n)+A₁ldrt₂(m, n))).

Verification of Controller Synthesis Based on Completely Specified Finite State Machine

Controller synthesis uses hardware description language and synthesis optimization tools from a higher abstract level. State transition graph of completely specified finite state machine is adopted to describe the behavior of controller. State transition graph STG_org was generated before synthesized and state transition graph STG_ext was reversely extracted from structure realization of controller synthesis. If STG_org and STG_ext were equivalent then corresponding process of controller synthesis was correct. The paper gives a formal verification algorithm of controller synthesis with time complexity O(B2/Aldrt1(n)+Aldrt2(m,n)) .In order to further improve time complexity of algorithm, a verifying algorithm with synthetic information guidance was proposed. The algorithm is proved efficient in theory for its time complexity is decreased to O(Bldrt1(n) + Aldrt2(m,n)).