Zhenhai Chen

A PVT insensitive boosted charge transfer for high speed charge-domain pipelined ADCs

A process, voltage, temperature (PVT) insensitive boosted charge transfer (BCT) circuit for charge-domain (CD) pipelined analog-to-digital converters (ADC) is presented. The output charge of existing BCT varies extensively with PVT variation, leading to large common-mode charge errors in each differential BCT stage when used in CD pipelined ADCs. Therefore, complicate common-mode control circuits must be adopted to stabilize the common-mode charge of each stage, which consumes large power and chip area. The proposed BCT circuit employs a differential difference amplifier and a differential voltage reference to reject the charge errors caused by PVT variations. A 125-MSPS, 10-bit CD pipelined ADC without common-mode control circuit is implemented based on the proposed BCT, consuming only 27mW from a 1.8V supply.

An embedded 14-bit 800MS/s DAC for direct digital frequency synthesizer in 0.18-μm CMOS

An embedded 14-bit 1-GS/s digital-to-analog converter for Direct Digital Frequency Synthesizer (DDFS) application is presented. The DAC is implemented using a segmented current-steering architecture, with the top 6bits and the remaining 8 bits. The output stage of dual return-to-zero scheme is used to enhance the dynamic performance of spurious-free dynamic range (SFDR). The DAC core is fabricated in a 1P6M 0.18 μm standard CMOS technology occupies a die area of only 1.6 × 1.5 mm2. The measured differential nonlinearity lies between −0.8 LSB and 0.3LSB, integral nonlinearity lies between −1.5LSB and 1LSB. And the SFDR is 76.47 dB for 80 MHz output at 0.8GHz sampling clock rate.

A low-power clock generator based on digital DLL for high speed pipelined ADCs

This paper presents a low-power clock generator based on digital delay locked loop (DLL) for high-speed and high-resolution analog-to-digital converters (ADCs). A novel structure for the phase detector and delay controller is adopted to eliminate dithering and false locking of the DLL. The operation frequency range of the DLL is 30MHz~250MHz, and the corresponding locking time is about 66.4us and 730ns, respectively. The proposed clock generator consumes 7.7mW from a 1.8-V power supply. A 250MSPS, 10-bit charge domain pipelined ADC adopting the DLL is fabricated in SMC 0.18μm CMOS process and achieves a SNDR of 56.7 dB.

A 27mW 10-bit 125MSPS charge domain pipelined ADC

A low power 10-bit 125-MSPS analog-to-digital converter (ADC) with MOS bucket-brigade devices (BBDs) based charge-domain (CD) pipelined architecture is described. A PVT insensitive boosted charge transfer (BCT) circuit is used in the design of the 10-bit CD pipelined ADC, which largely conquers the PVT variations sensitivity of the existing BCT circuit and eliminates the common mode charge control circuit and simplifies the system complexity of the existing CD pipelined ADCs. The prototype ADC is realized in a 0.18 μm CMOS process without using any common mode charge control techniques, with the power consumption of only 27mW at 1.8V supply and active die area of 1.04mm2. The prototype ADC achieves spurious free dynamic range (SFDR) of 67.7 dB, signal-to-noise ratio (SNDR) of 57.3 dB and effective number of bits (ENOB) of 9.0 for a 3.79 MHz input at full sampling rate. Differential nonlinearity (DNL) is +0.5/-0.3 LSB and integral nonlinearity (INL) is +0.7/-0.55 LSB.

A PVT insensitive BCT circuit with replica calibration for high speed charge-domain pipelined ADCs

A boosted charge transfer (BCT) circuit with replica calibration for high-speed charge domain (CD) pipelined analog to digital converters (ADCs) is presented in this paper. The common-mode charge errors caused by PVT variations can be rejected by the negative feedback network inside the replica circuit of the BCT. A 250-MSPS, 10bit CD pipelined ADC based on the proposed BCT achieves a SNDR of 56.7dB without digital calibration. The ADC is fabricated with SMC 0.18 μm CMOS process and consumes 150mW from a 1.8V power supply.