Zhenkun Yang

Validating direct memory access interfaces with conformance checking

Direct Memory Access (DMA) interfaces are a common and important component of Hardware/Software (HW/SW) interfaces between peripheral devices and their device drivers. We present a HW/SW co-validation framework to validate DMA interface implementations of a device and its driver. This framework employs a virtual prototype of the device as a reference model and performs co-validation in two stages: (1) conformance checking which checks the DMA interface conformance between the device and its virtual prototype; (2) property checking which checks device/driver interactions across the DMA interface. In conformance checking, the virtual prototype infers the device state transitions by taking the same driver request sequence to the device. Property checking verifies system properties over the device state transitions exposed through the virtual prototype. This framework assists HW/SW integration validation by detecting DMA interface bugs in both devices and drivers. Furthermore, we have developed three key techniques: capture-on-write policy, partial capture, and environmental input prediction, to address two major challenges in scaling the framework: DMA capture overhead and imprecise environmental input simulation. We have applied this approach to four Ethernet adapters, discovering 12 serious DMA interface bugs from the devices, their virtual prototypes and their drivers. The results demonstrate that our approach has major potential in facilitating HW/SW co-validation.

Automatic Modeling of Complex Functions with Clonal Selection-Based Gene Expression Programming

Gene expression programming (GEP) is a powerful evolutionary algorithm derived from genetic algorithm and genetic programming for system modeling and knowledge discovery. However, when dealing with complex problems, GEP shows quite slow convergence speed, it also probably encounters premature convergence. This paper proposed a clonal selection- based gene expression programming (CS-GEP), which combines the advantages of clonal selection algorithm (CSA) and GEP, overcoming some drawbacks of GEP. CS-GEP is applied into function modeling experiments, the results show that CS-GEP has faster convergence speed and higher modeling precision than that of GEP.

Handling design and implementation optimizations in equivalence checking for behavioral synthesis

Behavioral synthesis involves generating hardware design via compilation of its Electronic System Level (ESL) description to an RTL implementation. Equivalence checking is critical to ensure that the synthesized RTL conforms to its ESL specification. Such equivalence checking must effectively handle design and implementation optimizations. We identify two key optimizations that complicate equivalence checking for behavioral synthesis: (1) operation gating, and (2) global variables. We develop a sequential equivalence checking (SEC) framework to compare ESL designs with RTL in the presence of these optimizations. Our approach can handle designs with more than 32K LoC RTL synthesized from practical ESL designs. Furthermore, our evaluation found a bug in a commercial tool, underlining both the importance of SEC and the effectiveness of our approach.

Optimal components selection for analog active filters using clonal selection algorithms

In design and realization of analog electronic circuit, we usually use preferred value components, the performance of practical circuits often deviate from the ideal design target due to rounding the calculated component values to preferred ones. The best combination of the preferred value components exists in general, but the searching space of all combinations of preferred-value components is very huge. Clonal Selection Algorithms (CSA) is a widely used approach for handling optimization problems. In this paper, CSA is applied into searching optimal components for 4th order Butterworth filter design. Simulation results demonstrate that the proposed method is much superior to the conventional means. This method also can be applied into other types of filter design.

Automatic fault injection for driver robustness testing

Robustness testing is a crucial stage in the device driver development cycle. To accelerate driver robustness testing, effective fault scenarios need to be generated and injected without requiring much time and human effort. In this paper, we present a practical approach to automatic runtime generation and injection of fault scenarios for driver robustness testing. We identify target functions that can fail from runtime execution traces, generate effective fault scenarios on these target functions using a bounded trace-based iterative strategy, and inject the generated fault scenarios at runtime to test driver robustness using a permutation-based injection mechanism. We have evaluated our approach on 12 Linux device drivers and found 28 severe bugs. All these bugs have been further validated via manual fault injection. The results demonstrate that our approach is useful and efficient in generating fault scenarios for driver robustness testing with little manual effort.

Scalable Certification Framework for Behavioral Synthesis Front-End

Behavioral synthesis entails application of a sequence of transformations to compile a high-level description of a hardware design (e.g., in C/C++/SystemC) into a register-transfer level (RTL) implementation. In this paper, we present a scalable equivalence checking framework to validate the correctness of compiler transformations employed by behavioral synthesis front-end. Our approach makes use of dual-rail symbolic simulation of the input and output of a transformation, together with identification and inductive verification of their loop structures. We have evaluated our framework on transformations applied by an open source behavioral synthesis tool to designs from the CHStone benchmark. Our tool can automatically validate more than 75 percent of the total of 1008 compiler transformations applied, taking an average time of 1.5 seconds per transformation.

Equivalence checking for compiler transformations in behavioral synthesis

Behavioral synthesis entails application of a sequence of transformations to compile a high-level description of a hardware design (e.g., in C/C++/SystemC) into a Register-Transfer Level (RTL) implementation. We present a scalable equivalence checking framework to validate the correctness of compiler transformations employed by behavioral synthesis. Our approach is based on dual-rail symbolic simulation of the input and output design representations of a transformation. We have evaluated our framework on transformations applied to several designs by an open source behavioral synthesis tool, and we present initial results demonstrating the approach.

Coverage evaluation of post-silicon validation tests with virtual prototypes

High-quality tests for post-silicon validation should be ready before a silicon device becomes available in order to save time spent on preparing, debugging and fixing tests after the device is available. Test coverage is an important metric for evaluating the quality and readiness of post-silicon tests. We propose an online-capture offline-replay approach to coverage evaluation of post-silicon validation tests with virtual prototypes for estimating silicon device test coverage. We first capture necessary data from a concrete execution of the virtual prototype within a virtual platform under a given test, and then compute the test coverage by efficiently replaying this execution offline on the virtual prototype itself. Our approach provides early feedback on quality of post-silicon validation tests before silicon is ready. To ensure fidelity of early coverage evaluation, our approach have been further extended to support coverage evaluation and conformance checking in the post-silicon stage. We have applied our approach to evaluate a suite of common tests on virtual prototypes of five network adapters. Our approach was able to reliably estimate that this suite achieves high functional coverage on all five silicon devices.

Automated synthesis of passive analog filters using graph representation

In this paper, a novel method based on graph encoding scheme and clone selection algorithm is proposed for synthesizing passive analog filters. Graph is the most natural and convenient data structure to represent analog electronic circuit. The proposed graph-based encoding scheme can represent any topologies of passive analog circuit and their component values. Combined with the efficient analog circuit encoding scheme, clone selection algorithm is employed as a search engine for automatic design of passive analog filters. The proposed method can synthesize both topology and sizing (component parameters) of circuit simultaneously. Three filter design tasks are experimented to evaluate the proposed method. The experimental results demonstrate that passive analog filters can be generated effectively with modest computation time. Taking more practical conditions into account, the proposed method can be applied into automatic design of passive analog filters for engineering application without the guidance of experienced engineers.

Automatic synthesis of practical passive filters using clonal selection principle-based gene expression programming

This paper proposes a new method to synthesize practical passive filter using Clonal Selection principle-based Gene Expression Programming and binary tree representation. The circuit encoding of this method is simple and efficient. Using this method, both the circuit topology and component parameters can be evolved simultaneously. Discrete component value is used in the algorithm for practical implementation. Two kinds of filters are experimented to verify the excellence of our method, experimental results show that this approach can generate passive RLC filters quickly and effectively.