Zhigong Wang

5-Gb/s 0.18-/spl mu/m CMOS clock recovery circuit

A 5 Gb/s monolithic phase-locked clock recovery circuit is designed and realized in a 0.18 /spl mu/m CMOS technology. A half rate bang-bang phase detector and a multiphase oscillator incorporated with a charger-pump builds up half-rate phase-locked loop (PLL) architecture. The measured rms jitter of recovered clock signal is 4.7 ps under the stimulation of a 2/sup 11/-1-bit-long pseudorandom bit sequence at the bit rate of 5 Gb/s. The chip area is only 0.6 mm /spl times/ 0.6 mm and the DC power consumption is less than 90 mW under a single 1.8 V supply.

Design of bit-stream neuron based on direct Σ-Δ signal process

A novel method to build an artificial neuron is presented. All the modules in the artificial neuron are bit-stream units based on direct Σ-Δ signal process. The fundamental modules used in bit-stream artificial neuron, i.e., adder, multiplier, activation function unit, were implemented in integrated circuit (IC) form or Field Programmable Gate Array (FPGA). The principle, the structure and the performance of the modules are discussed.

A fully integrated low phase noise VCO for IEEE 802.11a WLAN transceivers in 0.18μm CMOS

A fully integrated voltage-controlled oscillator (VCO) for IEEE 802.11a WLAN transceivers is proposed and implemented in 0.18 μm CMOS technology with 1.8 V supply voltage. The VCO core adopts the topology of complementary cross-coupled differential inductance-capacitance (LC) tank. The VCO operates from 4.56 to 4.77 GHz with the varactor control voltage (Vtune) changing from 0.3 to 1.5 V and has a gain (Kv) of 175 MHz/V. A phase noise of -122.3 dBc/Hz at 1 MHz offset frequency is demonstrated for an oscillation frequency of 4.56 GHz. The average power consumption of this VCO is 30.24 mW.

Design of an active polyphase filter in GSM receiver with low-IF topologies

This paper describes the design of a polyphase filter in GSM receiver with low-IF topologies, using the circuit scheme of active-RC with the performance of single chip integrated. Based on TSMC 0.18 ¿m CMOS process, the Spectre simulation results indicate that the filter is centered at 110 kHz with 200 kHz of bandwidth. It has a voltage gain of about 30 dB, an image rejection ratio of about 38 dB. The power consumption is 4.2 mW under a 3 V power supply.

The implementation of 1-GHz bit-stream adder used in signal processing in a 0.18-μm CMOS technology

A kind of arithmetic and its implementation of bit-stream adder which can be used in digital signal processing were discussed in this paper. Compared with multi-bit adder, the bit-stream adder has the advantages of much simple structure and much small routing area. The ideal circuit model of the bit-stream adder was improved with a pipe line structure to make it work correctly in high frequency range. In order to increase the operating frequency, the physical circuit was deigned with the source coupled logic (SCL) technology. The IC was fabricated with TSMCs 0.18-μm CMOS process. The chip area is 475 μm ˜570 μm. The experimental results show that the function of the chip matches the demand of design and the chip can work at a frequency of higher than 1 GHz.

5 Gbps 0.35-/spl mu/m CMOS driver for laser diode or optical modulator

This paper presents a versatile driver for laser diode or optical modulator using a 0.35-/spl mu/m CMOS process. In this driver, a quasi push-pull source follower is introduced. Combined with a dynamic amplification technique, the drivers slew rate and output voltage swing are increased; meanwhile the overshoot is efficiently reduced. The driver works well at 2.5 Gbps under 3.3 V and 5 V supply voltage, consuming typical power of 310 mW and 945 mW respectively. It can give a modulation voltage (with 50-/spl Omega/ load) ranging from 0.55 V/sub P-P/ to 4.2 V/sub P-P/ under 3.3 V supply voltage and 0.6 V/sub p-p/ to 6.2 V/sub P-P/ under 5 V supply voltage, therefore it can be used as a laser diode or optical modulator driver. When the driver was tested with a LiNbO/sub 3/ modulator, clear optical eye diagrams were measured at 2.5 Gbps and 5 Gbps, respectively. The die area is 0.57 mm/sup 2/.

A 3.125-Gb/s CMOS word alignment demultiplexer for serial data communications

A cascaded 1:10 demultiplexer with comma detection and word alignment has been developed and fabricated using a 0.25/spl mu/m CMOS technology. It operates at half the clock frequency of the input data and uses a word alignment clock divider to ensure the parallel data output at the word boundary. Tested on wafer, the chip can operate from 1Gb/s to 3.125Gb/s to meet various specifications. The measured peak-peak voltage is above 700mV based on 50 /spl Omega/ load and the phase jitter are 11ps rms at the 3.125-Gb/s standard input bit rate. The power consumption is 234mW with a 3.3V supply and the chip area is 1.3mm/sup 2/.

IC for neural signal regeneration

Based on the 4-channels neural signal regeneration system which was realized by using discrete devices and successfully used for in-vivo experiments of rats and rabbits, an integrated circuit (IC) with 6-channels of neural signal regeneration has been designed and realized in CSMC¿s 0.6 ¿m CMOS technology. The IC consists of a neural signal amplifier with adjustable gain, a buffer stage, and a function electrical stimulation (FES) stage. The neural signal detecting circuit amplifies the detected weak signal come from the electrode to such a voltage that the FES circuit can be driven appropriately. The FES circuit amplifies the signal further so that the neural signal can be regenerated through the stimulating electrode. The neural signal regenerating IC occupies a die area of 2.82 mm×2.00 mm. Under double supply voltages of ±2.5 V, the DC power consumption is less than 50 mW. The on-wafer measurement results are as follows: the output resistor is 118 m¿, the 3 dB bandwidth is greater than 30 kHz, and the gain can be variable from 50 dB to 90 dB. The circuit has been used for in-vivo experiments on the rat¿s sciatic nerve as well as spinal cord with the cuff type electrode array or a needle twin-electrode, and the neural signal has been regenerated successfully both on a rat¿s sciatic nerve bundle and on a spinal cord.

A novel SPDT MEMS switch with isolation between bias and signal

A single-pole double throw (SPDT) radio frequency (RF) switching circuit is designed in a surface-micromachined, metal-metal contacting structure and fabricated in an RF MEMS (micro-electro-mechanical system) process. A folded cantilever beam is proposed to reduce the driving voltage. A dielectric layer is used to provide the isolation between the conductors of the bias and RF signal. Simulation results that in the frequency range from DC to 10 GHz the SPDT switch has an insertion loss of less 1 dB and an isolation of below -40 dB

A 3.3V SiGe HBT Power Amplifier for 5GHz WLAN Application

A monolithic integrated linear power amplifier (PA) for 5GHz WLAN application has been realized in 0.35mum-SiGe BiCMOS technology. The single-ended 3-stage power amplifier uses on-chip inductors and bond-wire inductance for input and interstage matching. Under a single supply voltage of +3.3V, the SiGe HBT MMIC power amplifier exhibits linear output power of 26.4dBm (P1dB), small signal gain of 24.7dB and the power added efficiency (PAE) of 29.2% at P1dB. The die size is only 1.2mmtimes0.8mm