Zhihua Dong

Overview of the QCDSP and QCDOC computers

The QCDSP and QCDOC computers are two generations of multithousand-node multidimensional mesh-based computers designed to study quantum chromodynamics (QCD), the theory of the strong nuclear force. QCDSP (QCD on digital signal processors), a four-dimensional mesh machine, was completed in 1998; in that year, it won the Gordon Bell Prize in the price/performance category. Two large installations--of 8,192 and 12,288 nodes, with a combined peak speed of one teraflops--have been in operation since. QCD-on-a-chip (QCDOC) utilizes a sixdimensional mesh and compute nodes fabricated with IBM systemon-a-chip technology. It offers a tenfold improvement in price/ performance. Currently, 100-node versions are operating, and there are plans to build three 12,288-node, 10-teraflops machines. In this paper, we describe the architecture of both the QCDSP and QCDOC machines, the operating systems employed, the user software environment, and the performance of our application-- lattice QCD.

QCDOC: A 10-teraflops scale computer for lattice QCD

Abstract The architecture of a new class of computers, optimized for lattice QCD calculations, is described. An individual node is based on a single integrated circuit containing a PowerPC 32-bit integer processor with a 1 Gflops 64-bit IEEE floating point unit, 4 Mbyte of memory, 8 Gbit/sec nearest-neighbor communications and additional control and diagnostic circuitry. The machines name, QCDOC, derives from “QCD On a Chip”.

Lattice QCD with eight light quark flavors

QCD with eight flavors is studied on 16[sup 3][times][ital N][sub [ital t]] lattices with [ital N][sub [ital t]]=4, 6, 8, 16, and 32, a dynamical quark mass [ital ma]=0.015, and lattice coupling [beta]=6/[ital g][sup 2] between 4.5 and 5.0. For [ital N][sub [ital t]]=16 and 32, hadron masses and screening lengths are computed for a variety of valence quark masses. The previously observed, strong, first-order transition for [ital N][sub [ital t]]=4, 6, and 8 is seen, for [ital N][sub [ital t]]=16, to become a [beta]-independent, zero-temperature transition characterized by a factor of [approx]3 change in lattice scale. This strong, first-order transition restores chiral symmetry, at least for [ital N][sub [ital t]]=4, 6, and 8, producing a chirally symmetric, weak-coupling phase. However, as [ital N][sub [ital t]] increases to 16, the chiral-symmetry properties of the weak-coupling side of the zero-temperature transition are unclear and offer a hint of a normal, finite-temperature, chiral-symmetry-breaking transition in the weak-coupling phase.

The QCD phase transition with four flavors of light quarks

Abstract We have performed four-flavor, full QCD simulations on 16 3 × N t lattices with N t = 4 and 6 and with quark masses ma = 0.01, 0.025, 0.0375 and 0.05 where a is the lattice spacing. For N t = 4 a first-order transition is seen for all four mass values and the chiral m →0 limit is easily recognized for the two lightest mass values. For N t = 6 we see a weak first-order transition for ma = 0.01 but find that it has disappeared for ma = 0.025 showing that the transition becomes more easily destabilized by the quark mass as the lattice spacing is reduced.

QCDOC: A 10 Teraflops Computer for Tightly-Coupled Calculations

Numerical simulations of the strong nuclear force, known as quantum chromodynamics or QCD, have proven to be a demanding, forefront problem in high-performance computing. In this report, we describe a new computer, QCDOC (QCD On a Chip), designed for optimal price/performance in the study of QCD. QCDOC uses a six-dimensional, low-latency mesh network to connect processing nodes, each of which includes a single custom ASIC, designed by our collaboration and built by IBM, plus DDR SDRAM. Each node has a peak speed of 1Gigaflops and two 12,288node, 10+ Teraflops machines are to be completed in the fall of 2004. Currently, a 512 node machine is running, delivering efficiencies as high as 45% of peak on the conjugate gradient solvers that dominate our calculations and a 4096-node machine with a cost of

HARDWARE AND SOFTWARE STATUS OF QCDOC.

1.6M is under construction. This should give us a price/performance less than

Status of the QCDOC project

1per sustained Megaflops.

Status of and performance estimates for QCDOC

QCDOC is a massively parallel supercomputer whose processing nodes are based on an application-specific integrated circuit (ASIC). This ASIC was custom-designed so that crucial lattice QCD kernels achieve an overall sustained performance of 50% on machines with several 10,000 nodes. This strong scalability, together with low power consumption and a price/performance ratio of

QCDOC: project status and first results

1 per sustained MFlops, enable QCDOC to attack the most demanding lattice QCD problems. The first ASICs became available in June of 2003, and the testing performed so far has shown all systems functioning according to specification. We review the hardware and software status of QCDOC and present performance figures obtained in real hardware as well as in simulation.

QCD phase structure with 8 light quark flavors

Abstract A status report is given of the QCDOC project, a massively parallel computer optimized for lattice QCD using system-on-a-chip technology. We describe several of the hardware and software features unique to the QCDOC architecture and present performance figures obtained from simulating the current VHDL design of the QCDOC chip with single-cycle accuracy.