Zhineng Fan

Ion-cut silicon-on-insulator fabrication with plasma immersion ion implantation

We report the implementation of ion-cut silicon-on-insulator (SOI) wafer fabrication technique with plasma immersion ion implantation (PIII). The hydrogen implantation rate, which is independent of the wafer size, is considerably higher than that of conventional implantation. The simple PIII reactor setup and its compatibility with cluster-tools offer other ion-cut process optimization opportunities. The feasibility of the PIII ion-cut process is demonstrated by successful fabrication of SOI structures. The hydrogen plasma can be optimized so that only one ion species is dominant. The feasibility of performing ion-cut using helium PIII is also demonstrated.

Separation by plasma implantation of oxygen (SPIMOX) operational phase space

Separation by plasma implantation of oxygen (SPIMOX) has been suggested as an economic alternative for separation by implantation of oxygen (SIMOX) to form the silicon-on-insulator (SOI) structure. The chief advantage of SPIMOX is the high throughput and low-cost implanter. The operation regime of implantation for SPIMOX, which uses dc plasma immersion ion implantation (PIII) for the oxygen implantation, has been studied in the phase space of implantation time and chamber pressure during implantation. The phase space is developed for a definite implantation voltage and dose which are dependent on the dimensions of the SOI structure to be fabricated. The effects of dose, implantation voltage, and fractional ionization on the phase space have been discussed. SPIMOX can achieve high throughputs for thin-SOI structure fabrications using high fractional ionization plasmas. The phase space developed for SPIMOX implantation ran also be used for other high-dose dc implantations with PIII which require a peaked implant profile below the surface.

Sample stage induced dose and energy nonuniformity in plasma immersion ion implantation of silicon

Plasma immersion ion implantation has been demonstrated to be a viable technique for microelectronics processing such as fabrication of shallow junction and silicon on insulator. However, a wider acceptance of this fledgling technology by the semiconductor industry is not possible unless the stringent dose and energy uniformity requirements can be met. We have recently discovered that the lateral dose and energy nonuniformity that is unacceptable to the silicon industry stems from the insulating shroud commonly used around the sample stage to reduce the current demand on the power supply. We have developed a theoretical model to explain the experimental results. The model can also be used to optimize the operating conditions and equipment design to achieve the desired dose and energy uniformity across a planar silicon wafer to satisfy the semiconductor industry.

Low pressure plasma immersion ion implantation of silicon

Mono-energetic plasma immersion ion implantation (PIII) into silicon can be attained only under collisionless plasma conditions. In order to reduce the current load on the high voltage power supply and modulator and sample heating caused by implanted ions, the plasma pressure must be kept low (<1 mtorr). Low pressure PIII is therefore the preferred technique for silicon PIII processing such as the formation of silicon on insulator. Using our model, we simulate the characteristics of low pressure PIII and identify the proper process windows of hydrogen PIII for the ion-cut process. Experiments are conducted to investigate details in three of the most important parameters in low pressure PIII: pulse width, voltage, and gas pressure. We also study the case of an infinitely long pulse, that is, dc PIII.

Thickness uniformity of silicon-on-insulator fabricated by plasma immersion ion implantation and ion cut

Plasma immersion ion implantation (PIII) is an economical means to implant a high dose of hydrogen into silicon and when combined with ion cut, has been demonstrated to be a viable technique to fabricate silicon-on-insulator (SOI). However, its success in the industry hinges on the quality of the SOI wafers produced. One of the most important parameters is the thickness uniformity of the SOI film. We have observed that the thickness variation across a 150 mm wafer follows a pattern in which the transferred silicon film is thickest in the center and thinnest near the edge. Alpha step and SIMS measurements indicate that the lateral nonuniformity is caused by the different penetration depths of hydrogen across the wafer. The experimental results can be explained quantitatively by an oblique incidence model.

In situ sample temperature measurement in plasma immersion ion implantation

Plasma immersion ion implantation (PIII) is an excellent surface modification technique because it is not restricted by the line-of-sight limitation that plagues conventional beamline ion implantation. However, the lack of in situ monitoring has hampered wider acceptance of the technique in industry. It is known that the implantation temperature has a large influence on the surface properties of the treated specimens in addition to the more obvious parameters such as implantation voltage, pulse duration, pulsing frequency, and so on. Direct measurement of the target temperature is complicated by the sample high voltage as well as by interference from the electromagnetic field and plasma. In this article, we present a novel interference-free, in situ temperature measurement technique employing a shielded thermocouple directly attached to the sample stage. Our experiments show that the setup can monitor the target temperature in real time, even under severe arcing conditions. Our results also indicate that ...

Surface metal contamination on silicon wafers after hydrogen plasma immersion ion implantation

Abstract Hydrogen plasma immersion ion implantation (PIII) in conjunction with ion-cut has been successfully utilized to fabricate silicon-on-insulator (SOI) wafers. In order for PIII to be accepted by the semiconductor industry as a commercial process, surface metal contamination that can affect device yield and properties must be minimized. Total-reflection X-ray fluorescence (TXRF) analysis of hydrogen PIII silicon wafers reveals surface iron contamination to be greater than 10 12 atoms/cm 2 . Even though ions bombard all surfaces in a PIII chamber and the sample stage is made of stainless steel, the small sputtering yield by hydrogen cannot fully account for the surface iron on the wafer. Further studies reveal that the sputtering contribution of ionized atmospheric species in the residual vacuum is significant. To minimize metal contamination in hydrogen PIII, the gas lines must be designed and sealed properly as outside air can easily leak into vacuum chamber due to the negative pressure inside the gas line.

Floating Low-temperature Radio-frequency Plasma Oxidation of Polycrystalline Silicon-germanium

Low temperature oxide formation is an important process in the fabrication of thin-film transistors (TFT) used in active-matrix liquid crystal displays. However, low temperature oxide is prone to have defects at the SiO2/polycrystalline–SiGe interfaces. We have recently developed a novel rf (radio frequency) plasma oxidation method for polycrystalline SiGe (poly-SiGe) materials. The poly-SiGe wafers are oxidized in an oxygen rf plasma with the samples electrically floating. That is, the sample voltage is the same as the sheath potential of the floating wall and is always negative with respect to the bulk of the plasma since electrons have higher mobility than ions. The slightly negative potential on the wafers attracts low energy oxygen ions from the plasma and the resulting damage on the wafers is thus lower than that induced by the more commonly used and energetic electron cyclotron resonance (ECR) source. No deliberate heating is applied during oxidation since the samples are heated spontaneously by th...

Operational phase-space of separation by plasma implantation of oxygen (SPIMOX)

SPIMOX using plasma immersion ion implantation (PIII) has been proposed as a cost-effective method for fabricating silicon on insulator (SOI) wafers. PIII, compared to conventional implanters, allows for simpler and low maintenance-cost implanters. High throughput, independent of the wafer size can be achieved by the SPIMOX process. A phase-space of implantation time and implantation pressure is developed to determine the operational regions for SPIMOX implantation. SPIMOX process using high fractional ionization plasma for implantation is found to be particularly suited for thin SOI fabrication required for future low-power IC applications.