Zhixiang Luo

Light waveguide electro-optical printed circuit board

The configuration of polymer light waveguide electro-optical printed circuit board(EOPCB) is proposed in this paper. An additional optical layer with light waveguide structure is used in conventional PCB to construct EOPCB. Light waveguide core layer mould is made with SU-8 photolithograph. Polymer light waveguide layer which is embedded between multiplayer PCB is made in experiment by Doctor-blading technology for large size application. Vertical cavity surface emitting laser (VCSEL) array is used as optical transmitter array. PIN photodiode array is used as optical receiver array. A MT-compatible direct coupling method is presented to couple light beam between optical transmitter/receiver with light waveguide layer. The optical signals from a processor element chip on the PCB can transmit to another processor element chip on the same PCB board through light waveguide interconnection in EOPCB. So optical interconnection between chip to chip for parallel multiprocessor system can be reailzed by EOPCB.

Photonic switching network for parallel multiprocessor cluster system using VCSEL laser arrays

A photonic switching network for parallel multiprocessor cluster system using vertical cavity surface emitting laser (VCSEL) arrays is described. The parallel multiprocessor cluster system provides 64 server nodes interconnected by optical interconnection network with parallel optical links. There are 8 cluster subsystems in the system. Each subsystem includes 8 computers and an optical interconnect backplane of 8x8 crossbar optical interconnection network with VCSEL-based optoelectronic I/O interface. An optical data transmission rate between computers is 5Gb/s which is transmifted by the optical fiber ribbon-based parallel optical data links with 2 channels at data rate of 2.5Gb/s per channel. Every I/O interface between optical interconnection network with each computer includes 16 VCSEL emitter pixels, 16 PIN receiver pixels. VCSEL emitter pixels transformed electrical signals from PCI bus of computer into optical signals, where PIN receiver pixels transformed optical signals from optical interconnect network backplane into electrical signals. The whole optical interconnection network is composed of two level optical interconnect backplanes. A total of 64 computers propagating for data communication of 8 subsystems would be realized.

3D optical interconnect mesh network for on-board parallel multiprocessor system based on EOPCB

A three-dimensional (3-D) 4×4×4 optical interconnect Mesh network scheme for parallel multiprocessor system based on polymer light waveguide electro-optical printed circuit board(EOPCB) is proposed in this paper. The Mesh topological structures of light waveguide interconnects for processor element chip-to-chip on a board, and board-toboard on backplane is constructed. The system consists of 64 processor element chips interconnected in a 3-D Mesh network configuration. Every processor board comprises 4x4 processor element chips with Mesh interconnection. Board-to-board Mesh interconnects are established on a backplane through light waveguide Mesh interconnect topological structure. An additional optical layer with light waveguide structure is used in conventional PCB to construct EOPCB. Vertical cavity surface emitting laser (VCSEL) array is used as optical transmitter array. PIN photodiode array is used as optical receiver array. A MT-compatible direct coupling method is presented to couple light beam between optical transmitter/receiver with light waveguide layer. The optical signals from a processor element chip on a board can transmit to another processor element chip on another board through light waveguide interconnection in the backplane. So 3-D optical interconnection Mesh network for parallel multiprocessor system can be reailzed by EOPCB.

Photonic switching network with VCSEL array packaging for parallel multiprocessor cluster system

A novel photonic switching network with vertical cavity surface emitting laser (VCSEL) array packaging for parallel multiprocessor cluster system is described. The parallel multiprocessor cluster system provides 64 serve nodes connected by photonic switching network with parallel optical links. There are eight cluster subsystems in the system. Each subsystem includes eight computing nodes and an optical interconnect backplane of 8x8 crossbar optical interconnection network with VCSEL-based optoelectronic I/O parallel interface. Every I/O parallel interface between optical interconnection network and every computing node includes 16 VCSEL emitter pixels, 16 PIN receiver pixels. In order to couple 16 signal light beam array into optical fiber array ribbon, a fabrication technique based on the high precise position slot is used for assembling optical fiber array interface. A packaging structure for optical fiber array interface is presented. As the position slots of optical fiber array interface are formed by VLSI photolithography and IcP etch techniques, and etching depth is smaller compared with V-groove slot, the high precision slots with 25Ojtm pitch can be obtained. A configuration of coupling packaging for 16 VCSEL pixel array to 16 fiber array with 45° end surface is also presented in this paper.

Design and evaluate an architecture of a growable packet switch

This paper focuses on the problem of designing a large 256×256 high-performance broadband packet (or ATM) switch. Early packet switch research concentrated on using N×log2N structures with buffers at each switch element. As a result, the nude number and the cost of such kinds of switches become prodigious and consequently could not have more practical significance. In this paper, we provide a method to design a kind of architecture containing fewer nodes. The distribution network of this new architecture based on the knockout theory has very low internal blocking, similar to that found in large 256×256 single crossbar networks, but the complexity and cost are less than that of single crossbar networks. A Balanced Incomplete Block Design (BIBD) in Combinatorics is provided to help construct the architecture. With this method, the mapping function between the input ports and the crossbars can be realized by a serial of mutually orthogonal Latin Squares (MOLS). Moreover, statistical tools are used to calculate the possibility of internal blocking of the network and to make a comparison between the improved architecture and the common one.

Cluster system using fiber channel as an interconnection network analysis

In the parallel processing system, large numbers of processors are interconnected in order to improve the performance of the computer, such as the symmetric multiprocessor (SMP) architecture. When the basic node is an SMP or a computer having a single processor, the characteristics of an interconnection networks are important factors which influence the performance of the entire system. Fibre Channel (FC) has a lot advantages, such as excellent scalability; the bandwidth is large; delay time is short and fault tolerance is large. It is assumed that an SMP is used for a basic node. We construct the cluster system using FC as interconnection network, which are a fabric method and a FC Arbitrated Loop (FC-AL) method. According the method, if the number of nodes supported by the interconnection network is small, the addition of extra nodes can be added at small expense. The bandwidth of each node is large, the delay time is short, and the fault tolerance effect is large in the interconnection network. In the case of connecting to a shared disk, a large bandwidth is provided and time required for gaining access to the shared disk becomes short.

OC-192 very short reach (VSR) parallel optical interconnect demonstrated system

This paper describes the design of an OIF-approved 10Gbps very short reach parallel optical interconnect demonstrated system. It is a 12x1.25Gb/s channel parallel optics solution, leveraging the low cost transceiver (850nm VCSEL), and CMOS (SERDES) technologies originally developed for Gigabit Ethernet. The demonstrator comprises of SONET/SDH serial OC-192 interface, CPLD based convert IC, 1.25Gbps 12-channel parallel optical transmitter and receiver. The transmitter includes a 12-channel array of 850nm VCSEL, a 12-channel VCSEL driver LSI, and a precise coupling structure for 12 multi-mode-fibers ribbon. The receiver consists of a 12-channel array of pin-PDs, a 12-channel receiver LSI, and a precise coupling structure for 12 multi-mode-fibers ribbon. A CPLD chip, which maps the OC-192 framer onto the parallel optical links, and reassembles it after detection, has been developed. We also present the coupling package configuration for VCSEL arrays to fiber ribbon.

Optical switch network for a multiprocessor cluster system of 128 nodes

A novel hybrid electrical optical Clos switch network for multiprocessor cluster system was presented. For multiprocessor cluster system of 128 hosts, the novel optical Clos network includes 16 basic modules, a passive optical fiber backplane with (8×15)×16 which has a total of 1920 optical data channels and a signaling control system. The basic module is composed of the input line cards of 8 hosts, a single chip of 16×16 crossbar switch, parallel transmitting VCSEL modules for fan-out of (16-1)optical fiber channels and (16-1)×1 optical combiners. The passive optical fiber backplane of very large capacity and high density, based on linear VCSEL arrays and fiber ribbon technology, is to be used to interconnect between hosts of different sub-clusters. The routing of the optical Clos switch network is decided by a signaling control system. Compared with high performance electronic system, this technology offers a relatively easy and simple means of communicating large amount of information between hosts, and lower delay time.

Optical interconnection network with parallel optical links for multiprocessor cluster system of 256 nodes

An optical interconnection network with parallel optical links for multiprocessor cluster system of 256 nodes is described. There are 16 subsystems in the system, in which each subsystem includes 16 computers and an optical fiver-ribbon interconnection plate of 16X16 crossbar interconnection network with VCSEL-based opto-electronic interface. An optical data rate between computers is 5Gb/s which is transmitted by the optical fiber-ribbon based parallel optical data links with 4 channels at data rates of 1.25Gb/s per channel. Every interface between optical interconnection network and each computer includes 16X4 VCSEL pixels, 16X4 PIN pixels and (1X16)X4 electrical switch. The whole optical interconnection network is composed of two level optical networks. There are sixteen optical fiber-ribbon interconnection plates of 16X16 crossbar interconnection network in the bottom level. The top level optical interconnection network would be an optical fiber-ribbon interconnection plate with a total of 2084 data channels propagating for communication of 16 subsystems.