Zhixing Zhao

RF CMOS Parametric Downconverters

Parametric amplifiers are absent today from the majority of electronics applications. This is especially the case for parametric downconverters (PDCs). Coupled with the increasing emphasis on millimeter-wave applications and the cost of transistor scaling, the time may be right to reconsider these circuits. By employing coupled-mode theory, we arrive at a general description of PDCs. Consequently, a simple mixer is proposed that achieves gain at reduced pumping frequencies without resorting to sub-harmonics. The implications of this design for quadrature receiver systems are shown. Fundamental gain and noise limits are derived indicating the ability to operate at sub-5-dB noise figures (NFs) with very low-power requirements. Measurements on an accumulation-mode varactor in 130-nm CMOS technology indicate the necessary pumping and biasing regimes needed to approach these limits. Finally, a compact 30-GHz PDC design with 2-dB NF is discussed.

100 GHz Parametric CMOS Frequency Doubler

A parametric MOS varactor-based integrated frequency doubler is reported. The circuit is implemented in 130 nm CMOS but uses a conservative 0.35 μm gate length and produces an output between 94 and 108 GHz with a minimum measured conversion loss of 14.5 dB and a maximum output power of -7.5 dBm. Slow-wave transmission line filters are employed to reduce circuit loss and the area required by the chip.

Compact parametric downconversion using MOS varactors

IC Parametric mixers built in CMOS are a promising means of realizing high-gain, low-noise and low-power RF heterodyne downconverters. This paper looks at two known parametric topologies and discusses a new approach intended to simplify the LO. Measured MOS varactor data is used to demonstrate the feasibility of mixers with 10-dB gain, sub 5-dB NFs and power requirements below 1-mW at microwave frequencies.

Parametric CMOS upconverters and downconverters

This paper discusses parametric CMOS mixers as potential radio-frequency front-end contributors to advanced mm-wave and sub-mm-wave wireless communicators. It outlines fundamental concepts underlying parametric circuit operation highlighting its benefits with regards to power consumption, speed, and noise performance. The implementation of parametric CMOS architectures is detailed. Critical device properties and figures of merit are shown. Measurement results of prototype designs are given. Copyright

Coherent parametric RF downconversion in CMOS

Parametric circuits constitute a longstanding RF technique that has been largely ignored by the RFIC community. Increasing interest in applying CMOS to (sub)millimeter-wave applications plus mounting scaling complexity may combine to revitalize this circuit style. This paper presents basic parametric downconverter structures, their theory of operation, and the benefits to be gained from CMOS implementation. A low-power, sub-1-V, fully integrated mixer in 130-nm CMOS is introduced. It implements two parametric modes and operates on RF signals between 22 and 24 GHz with possible conversion gains in excess of 20 dB.

A Direct 100 GHz Parametric CMOS Tripler

The first direct anti-series CMOS tripler is described in this letter. MOS varactors are arranged in a back-to-back configuration free of the self-bias problem that prevents standard Schottky varactors from employing such an arrangement. Implemented in 130 nm CMOS, the circuit achieves a 28 dB conversion loss at 102 GHz with an output power of -20 dBm.

A 0.13-µm CMOS wireless reflector for phase sweep cooperative diversity

A 4-GHz 1.2-V all-analog wireless reflector acting as a cooperative diversity repeater is built in 0.13-μm CMOS technology. Interfaced with a dipole antenna, the circuit achieves 22.3-dB gain for a low power consumption equal to 120 μW. By applying slow phase sweeping at the reflector node, diversity gain is achieved and the coverage area of an indoor wireless network is increased by a factor of 2.5.

35.5 GHz Parametric CMOS Upconverter

Parametric circuit techniques are a promising means of applying CMOS to millimeter-wave (mm-wave) and sub-mm-wave front-ends. However, almost no experimental results are available for these circuits in modern silicon technologies. In this letter, a parametric 0.5-to-35.5 GHz upconverter based on an accumulation-mode MOS varactor (AMOSV) is implemented in 0.13 μm CMOS technology. It achieves a maximum conversion gain of 14 dB in the upper sideband (USB) configuration and 13 dB in the lower sideband (LSB) configuration with no dc power consumption. In the design, on-chip slow-wave coplanar waveguide interconnections are used for reducing layout area.

Parametric THz frequency multiplication using CMOS technology

Accumulation-mode MOS varactors (AMOSVs) are considered for use in THz frequency multipliers. The superior modulation ratios and lower series loss relative to silicon Schottky diodes for a 130-nm CMOS technology are highlighted. Dynamic cutoff frequencies in excess of 1-THz are predicted. AMOSV potential for 10-dB loss, 600-GHz doublers is discussed as is an integrated 100-GHz doubler design.

Implementation of an all-analog active reflector

A 3.65-GHz all-analog wireless reflector acting as a cooperative diversity repeater is built in 0.13-μm CMOS technology and its performance is evaluated. Interfaced with a folded dipole antenna, the circuit can achieve a 23.5-dB gain for a very low power consumption equal to 300 μW.