Zhiyong He

Highly-Parallel Decoding Architectures for Convolutional Turbo Codes

Highly parallel decoders for convolutional turbo codes have been studied by proposing two parallel decoding architectures and a design approach of parallel interleavers. To solve the memory conflict problem of extrinsic information in a parallel decoder, a block-like approach in which data is written row-by-row and read diagonal-wise is proposed for designing collision-free parallel interleavers. Furthermore, a warm-up-free parallel sliding window architecture is proposed for long turbo codes to maximize the decoding speeds of parallel decoders. The proposed architecture increases decoding speed by 6%-34% at a cost of a storage increase of 1% for an eight-parallel decoder. For short turbo codes (e.g., length of 512 bits), a warm-up-free parallel window architecture is proposed to double the speed at the cost of a hardware increase of 12%

A class of irregular LDPC codes with low error floor and low encoding complexity

In this letter, we propose a class of irregular structured low-density parity-check (LDPC) codes with low error floor and low encoding complexity by designing the parity check matrix in a triangular plus dual-diagonal form. The proposed irregular codes clearly lower the error floor and dramatically improve the performance in the waterfall region of error-rate curves. Being characterized by linear encoding complexity, the encoders of the proposed codes attain throughputs over 10 Gbit/s.

FPGA Implementation of LDPC Decoders Based on Joint Row-column Decoding Algorithm

This paper presents a joint row-column decoding algorithm for the decoding of low-density parity-check (LDPC) codes. Simulation indicates that the proposed algorithm improves the performance in both the waterfall region and the error floor region. By combining row processing with column processing, the joint row-column decoding algorithm reduces the storage requirements of extrinsic messages and avoids memory conflicts and routing congestion during the exchanges of extrinsic messages. Implementation results into field programmable gate array (FPGA) devices indicate that the proposed algorithm reduces the hardware costs by 30% and increases the decoding speed by a factor of four. A 40-parallel decoder attains a throughput of 2 Gbits/sec by using up to 20 % of the generic logic resources in a Xilinx XC4LX160 device

Lowering Error Floor of LDPC Codes Using a Joint Row-Column Decoding Algorithm

Low-density parity-check codes using the belief-propagation decoding algorithm tend to exhibit a high error floor in the bit error rate curves, when some problematic graphical structures, such as the so-called trapping sets, exist in the corresponding Tanner graph. This paper presents a joint row-column decoding algorithm to lower the error floor, in which the column processing is combined with the processing of each row. By gradually updating the pseudo-posterior probabilities of all bit nodes, the proposed algorithm minimizes the propagation of erroneous information from trapping sets into the whole graph. The simulation indicates that the proposed joint decoding algorithm improves the performance in the waterfall region and lowers the error floor. Implementation results into field programmable gate array (FPGA) devices indicate that the proposed joint decoder increases the decoding speed by a factor of eight, compared to the traditional decoder.

Origins of intermediate velocity particle production in heavy ion reactions

In this paper, we report for the first time clear distinctions between these prompt processes and an alternative phenomenon of delayed aligned asymmetric breakup that populates the intermediate-velocity zone by a deformation rupture of mainly the heavier of the colliding partners in mass asymmetric collisions. These distinctions were observed experimentally with intermediate-velocity particle correlation analysis of Ni+C and Ni+Au reac

Encoder architecture with throughput over 10 Gbit/sec for quasi-cyclic LDPC codes

This paper discusses the design of a high-speed encoder for low density parity check (LDPC) codes. To minimize hardware costs and memory requirements of such encoders, a class of high-performance quasi-cyclic LDPC codes which can be encoded in linear time has been proposed by designing the parity check matrix in a triangular plus dual-diagonal form. Based on the proposed codes, parallel architectures and pipelining technology have been used to increase the throughput of encoders. Moreover, collisions which occur when parallel processors contend for write access to the same memory module are avoided by exploiting an iterative encoding approach which involves repeated usage of the processors. The implementation results into field programmable gate array (FPGA) devices indicate that the encoder for the LDPC code with a block length of 2048 and a code rate of 0.5 attains a throughput of 12.8 Gbit/s using 352 exclusive-OR gates

LDPC Coded Wireless Networks with Adaptive Spectral Efficiency

Low-density parity-check (LDPC) codes offer a very powerful error correction technique which allows data transmission in wireless networks at rates near the channel capacity with arbitrarily low probability of error. In this paper, we design a class of linearly encodable LDPC codes with adaptive code rates, i.e. the code rate can be adapted according to channel conditions to maximize the total capacity. Since a unique mother parity check matrix is used to construct LDPC codes with several code rates, the great advantage of the proposed codes is that a single universal encoder (decoder) is adequate to encode (decode) multi-rate codes, which makes it possible to efficiently implement multi-rate LDPC codes in a subscriber station. The implementation results into field programmable gate array (FPGA) devices indicate that a universal layered encoder for LDPC codes with 9 code rates is capable of reaching a throughput above 1.2 Gigabit per second by using 138 exclusive- OR gates and a master clock of 100 MHz. By combining multilevel modulation with the designed multi-rate LDPC codes, a transmission scheme with adaptive spectral efficiency is proposed. The simulation results indicate that the schemes with a spectral efficiency of 1, 2, 3, 4, and 5 bits/symbol/Hz can achieve extremely reliable transmission in a Rayleigh fading channel at signal-to-noise ratios (SNR) per bit of 5, 6, 10, 14, and 16 dB, respectively.

A BGO detector array and its application in intermediate energy heavy ion experiments

A BGO crystal (Bi4Ge3O12) as the E detector of ΔE-E for identification of reaction products has been used for detecting the charged particles emitting from the 25 MeV/u 40Ar induced reaction. The responses of the BGO crystal to various light charged particles were measured. A close-packed hexagonal array consisting of thirteen ΔE-E telescopes (Si-BGO) has been developed to detect the light charged particles interfering with each other in intermediate-energy heavy-ion induced reactions. Some applications of this telescope array are also described.

Adaptive LDPC codes for MIMO transceiver with adaptive spectral efficiency

By using a multi-rate low density parity check (LDPC) code, we propose an LDPC coded multiple-input multiple-output (MIMO) transceiver with adaptive spectral efficiency which allows data transmission in wireless networks at rates near the channel capacity with arbitrarily low probability of error. Equipped with multiple transmit and multiple receiver antennae, the proposed LDPC coded MIMO transceiver can maximize either coding gain with space-time diversity technique or channel capacity with space-time multiplexing technique. Since the proposed multi-rate LDPC code is constructed based on a single master parity check matrix using a row-removing approach, a single universal encoder (decoder) suffices to handle all rates. Thus, the proposed approach makes the proposed scheme feasible in a subscriber station, such as a cellular phone, to maximize the total channel capacity with a guaranteed quality-of-service. The simulation results indicate that an LDPC coded MIMO transceiver with a spectral efficiency of 1, 2, 3, 4, and 5 bits/symbol/Hz can achieve extremely reliable transmission in a Rayleigh fading channel at the signal-to-noise ratio (SNR) per bit of -2.5, 0.25, 2, 4.75, and 6.5 dB, respectively, when two transmit and two receiver antennae are used for space-time diversity.

An encoder/decoder with throughput over Gigabits/sec for rate-compatible LDPC codes with wide code rates

A challenge in the design of rate-compatible (RC) low-density parity-check (LDPC) codes is how to maximize the range of code rates. In this paper, we propose a class of RC LDPC codes with a very wide range of code rates. To ensure linear encoding, dual-diagonal form for the parity part of the mother parity-check matrix is used. Constructed from shifted identity matrices, the proposed codes are particularly well-suited for the high-speed implementation of parallel encoders and parallel decoders. To widen the range of code rates, we have proposed an optimal transmission scheme, which keeps the optimal degree distribution unchanged for the mother code and all daughter codes. Thus, the proposed technique pushes the upper bound of code rates to 0.96, which is the highest rate in RC LDPC codes in the world, based on our best knowledge. The implementation results into field programmable gate array (FPGA) devices indicate that a parallel encoder (decoder) for the proposed RC LDPC codes is capable of reaching a throughput of 7.2 (1.8) Gigabits per second using a clock frequency of 150 MHz.