Zhuang Yiqi

Tax forecasting theory and model based on SVM optimized by PSO

The construction of tax forecasting model is difficult due to its uncertain, non-linear, dynamic and complicated characteristics. It is difficult to describe the non-linear characteristics of tax forecasting by traditional methods. In the study, the novel forecasting method based on the combination of support vector machine (SVM) and particle swarm optimization (PSO) is proposed to the tax forecasting. The non-linear relationship in tax forecasting is efficiently represented by support vector machine, and particle swarm optimization is used to select the training parameters of support vector machine. The tax forecasting model is constructed by support vector machine optimized by particle swarm optimization (PSVM) on the basis of research for the proposed forecasting model. The tax forecasting cases are used to testify the forecasting performance of the proposed model. The experimental results demonstrate that the proposed PSVM model has good forecasting performance.

New analytical threshold voltage model for halo-doped cylindrical surrounding-gate MOSFETs

Using an exact solution of two-dimensional Poissons equation in cylindrical coordinates, a new analytical model comprising electrostatic potential, electric field, threshold voltage and subthreshold current for halo-doped surrounding-gate MOSFETs is developed. It is found that a new analytical model exhibits higher accuracy than that based on parabolic potential approximation when the thickness of the silicon channel is much larger than that of the oxide. It is also revealed that moderate halo doping concentration, thin gate oxide thickness and small silicon channel radius are needed to improve the threshold voltage characteristics. The derived analytical model agrees well with a three-dimensional numerical device simulator ISE.

A two-dimensional analytical subthreshold behavior model for junctionless dual-material cylindrical surrounding-gate MOSFETs

A two-dimensional analytical subthreshold behavior model for junctionless dual-material cylindrical surrounding-gate (JLDMCSG) metal-oxide-semiconductor field-effect transistors (MOSFETs) is proposed. It is derived by solving the two-dimensional Poissons equation in two continuous cylindrical regions with any simplifying assumption. Using this analytical model, the subthreshold characteristics of JLDMCSG MOSFETs are investigated in terms of channel electrostatic potential, horizontal electric field, and subthreshold current. Compared to junctionless single-material cylindrical surrounding-gate MOSFETs, JLDMCSG MOSFETs can effectively suppress short-channel effects and simultaneously improve carrier transport efficiency. It is found that the subthreshold current of JLDMCSG MOSFETs can be significantly reduced by adopting both a thin oxide and thin silicon channel. The accuracy of the analytical model is verified by its good agreement with the three-dimensional numerical simulator ISE TCAD.

Model of radiation-induced gain degradation of NPN bipolar junction transistor at different dose rates*

Ionizing-radiation-induced current gain degradation in NPN bipolar junction transistors is due to an increase in base current as a result of recombination at the surface of the device. A model is presented which identifies the physical mechanism responsible for current gain degradation. The increase in surface recombination velocity due to interface states results in an increase in base current. Besides, changing the surface potential along the base surface induced by the oxide-trapped charges can also lead to an increased base current. By combining the production mechanisms of oxide-trapped charges and interface states, this model can explain the fact that the current gain degradation is more severe at a low dose rate than at a high dose rate. The radiations were performed in a Co60 source up to a total dose of 70 krad(Si). The low dose rate was 0.1 rad(Si)/s and the high dose rate was 10 rad(Si)/s. The model accords well with the experimental results.

A digitally controlled AGC loop circuitry for GNSS receiver chip with a binary weighted accurate dB-linear PGA

A novel digitally controlled automatic gain control (AGC) loop circuitry for the global navigation satellite system (GNSS) receiver chip is presented. The entire AGC loop contains a programmable gain amplifier (PGA), an AGC circuit and an analog-to-digital converter (ADC), which is implemented in a 0.18 μm complementary metal-oxide-semiconductor (CMOS) process and measured. A binary-weighted approach is proposed in the PGA to achieve wide dB-linear gain control with small gain error. With binary-weighted cascaded amplifiers for coarse gain control, and parallel binary-weighted trans-conductance amplifier array for fine gain control, the PGA can provide a 64 dB dynamic range from −4 to 60 dB in 1.14 dB gain steps with a less than 0.15 dB gain error. Based on the Gaussian noise statistic characteristic of the GNSS signal, a digital AGC circuit is also proposed with low area and fast settling. The feed-backward AGC loop occupies an area of 0.27 mm2 and settles within less than 165 μs while consuming an average current of 1.92 mA at 1.8 V.

A power-efficient 12-bit analog-to-digital converter with a novel constant-resistance CMOS input sampling switch

A power-efficient 12-bit 40-MS/s pipeline analog-to-digital converter (ADC) implemented in a 0.13 μm CMOS technology is presented. A novel CMOS bootstrapping switch, which offers a constant on-resistance over the entire input signal range, is used at the sample-and-hold front-end to enhance the dynamic performance of the pipelined ADC. By implementing with 2.5-bit-per-stage and a simplified amplifier sharing architecture between two successive pipeline stages, a very competitive power consumption and small die area can be achieved. Meanwhile, the substrate-biasing-effect attenuated T-type switches are introduced to reduce the crosstalk between the two opamp sharing successive stages. Moreover, a two-stage gain boosted recycling folded cascode (RFC) amplifier with hybrid frequency compensation is developed to further reduce the power consumption and maintain the ADCs performance simultaneously. The measured results imply that the ADC achieves a spurious-free dynamic range (SFDR) of 75.7 dB and a signal-to-noise-plus-distortion ratio (SNDR) of 62.74 dB with a 4.3 MHz input signal; the SNDR maintains over 58.25 dB for input signals up to 19.3MHz. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.43 to +0.48 LSB and −1.62 to +1.89 LSB respectively. The prototype ADC consumes 28.4 mW under a 1.2-V nominal power supply and 40 MHz sampling rate, transferring to a figure-of-merit (FOM) of 0.63 pJ per conversion-step.

A Method to Enhance the Throughput Performance of Bluetooth 2.0+EDR Specification

Propose a method adding 2-DM and 3-DM packets to the Bluetooth 2.0+EDR specification to improve data transmission performance. The anafysis is exact under the channef of AWGN and assumes the channel remains stationary for the duration of each packet. By selecting appropriate packet type to transmit in different SNRs, maximum throughput can be obtained. Simulation result shows that adding 2-DM and 3-DM packets to Bluetooth 2.0+EDR specification will improve the anti- interference ability and enhance data transmission throughput greatly in AWGN channel.

1f noise as a prediction of long-term instability in integrated operational amplifiers

Abstract It is shown from the accelerated life test and noise measurement that the long-term instability of integrated operational amplifiers due to the drift of input bias/offset current is strongly correlated with 1 f noise in the devices, and the current drift is approximately proportional to 1 f noise current measured before the test. In the mechanism analysis, the instability and the 1 f noise may be attributed to the same physical source and both are caused by the modulation of oxide traps to Si surface carriers. 1 f noise measurement may therefore be applied as a fast and nondestructive tool to predict the long-term instability of operational amplifiers.

Vertical-dual-source tunnel FETs with steeper subthreshold swing*

In order to improve the drive current and subthreshold swing (SS), a novel vertical-dual-source tunneling field-effect transistor (VDSTFET) device is proposed in this paper. The influence of source height, channel length and channel thickness on the device are investigated through two-dimensional numerical simulations. Si-VDSTFET have greater tunneling area and thinner channel, showing an on-current as high as 1.24 μA at gate voltage of 0.8 V and drain voltage of 0.5 V, off-current of less than 0.1 fA, an improved average subthreshold swing of 14 mV/dec, and a minimum point slope of 4 mV/dec.

Analytical modeling of the direct tunneling current through high-k gate stacks for long-channel cylindrical surrounding-gate MOSFETs

An analytical direct tunneling gate current model for cylindrical surrounding gate (CSG) MOSFETs with high-k gate stacks is developed. It is found that the direct tunneling gate current is a strong function of the gates oxide thickness, but that it is less affected by the change in channel radius. It is also revealed that when the thickness of the equivalent oxide is constant, the thinner the first layer, the smaller the direct tunneling gate current. Moreover, it can be seen that the dielectric with a higher dielectric constant shows a lower tunneling current than expected. The accuracy of the analytical model is verified by the good agreement of its results with those obtained by the three-dimensional numerical device simulator ISE.