Zitao Shi

Concurrent Design Analysis of High-Linearity SP10T Switch With 8.5 kV ESD Protection

This paper discusses concurrent design and analysis of the first 8.5 kV electrostatic discharge (ESD) protected single-pole ten-throw (SP10T) transmit/receive (T/R) switch for quad-band (0.85/0.9/1.8/1.9 GHz) GSM and multiple-band WCDMA smartphones. Implemented in a 0.18 μm SOI CMOS, this SP10T employs a series-shunt topology for the time-division duplex (TDD) transmitting (Tx) and receiving (Rx), and frequency-division duplex (FDD) transmitting/receiving (TRx) branches to handle the high GSM transmitter power. The measured P0.1 dB, insertion loss and Tx-Rx isolation in the lower/upper bands are 36.4/34.2 dBm, 0.48/0.81 dB and 43/40 dB, respectively, comparable to commercial products with no/little ESD protection in high-cost SOS and GaAs technologies. Feed-forward capacitor (FFC) and AC-floating bias techniques are used to further improve the linearity. An ESD-switch co-design technique is developed that enables simultaneous whole-chip design optimization for both ESD protection and SP10T circuits.

Design and Analysis of Vertical Nanoparticles-Magnetic-Cored Inductors for RF ICs

We report the design and analysis of the first vertical magnetic-cored inductors in CMOS backend for radio-frequency (RF) ICs, which includes theoretical and experimental studies of device architecture, equivalent circuit model with parameter extraction technique, process development, and device characterization. Vertical magnetic cores with multiple-layer stacked-spiral structures are designed to realize compact inductive devices in RF ICs. A CMOS-compatible post-CMOS backend process module (CMOS +) and optimized high-permeability nanoparticles are utilized to achieve a high inductance-to-coil-area ratio (L-density) in gigahertz range. The prototype six-layer inductors with NiZnCu ferrite nanoparticles-magnetic-core were fabricated in a commercial foundry 0.18-μm six-metal RF CMOS technology. A high L-density of over 700 nH/mm2 to multigigahertz was obtained, with an 80% chip size reduction from the reference planar magnetic inductors. An equivalent circuit model with parameter extraction technique is developed to analyze magnetic enhancement effects. This work demonstrates the potential of design and integration of compact high-performance vertical magnetic-cored inductive devices into CMOS backend for high-quality and low-cost RF systems-on-a-chip.

Dual-Direction Nanocrossbar Array ESD Protection Structures

This letter reports a new nanocrossbar array ESD protection design. The unique nanocrossbar array structures ensure uniform ESD discharging and achieve fast ESD response speed and >; 8A ESD protection capability in prototypes. The nanoswitching ESD protection effect eliminates large leakage current inherent to traditional p-n-junction-type ESD protection devices.

Programmable On-Chip ESD Protection Using Nanocrystal Dots Mechanism and Structures

This paper reports a new nanocrystal quantum-dot (NC-QD)-based tunable on-chip electrostatic discharge (ESD) protection mechanism and structures. Experiments validated the programmable ESD protection concept. Prototype structures achieved an adjustable ESD triggering voltage range of 2.5 V, very fast response to ESD transients of rising time tr ~ 100 ps and pulse duration td; ~ ns, ESD protection density of 25 mA/μm in human body model and 400 mA/μm in charged device model equivalent stressing, and a very low leakage current of Ileak ~ 15 pA. The NC-QD ESD protection concept can potentially be used to design field-programmable on-chip ESD protection circuitry for mixed-signal ICs in nanoscales.

Novel Nanophase-Switching ESD Protection

This letter reports the proof-of-concept results for the new nontraditional nanophase-switching electrostatic-discharge (ESD) protection mechanism and nanocrossbar ESD structures. Experiment shows good ESD switching and protection, i.e., a fast response of 100 ps, a ultralow leakage of 0.26 pA, and an ESD protection of >; 267 V/μm2. A new dispersed local ESD tunneling model is proposed, and heterogeneous complementary metal-oxide-semiconductor integration is developed.

Stacked-spiral RF inductors with vertical nano-particle-magnetic-medium

A new concept of stacked-spiral inductor with vertical near-closed-circuit nano-particle-magnetic-core in CMOS is reported. Prototypes, fabricated in a 6-Al-metal CMOS backend process using ferrite nano-particles, show a high inductance-density of 825nH/mm2 in multi-GHz, which is promising for making super compact inductors in RF SoC.

Nano crystal quantum dots tunable on-chip ESD protection

This paper reports a new nano crystal quantum dots (NC-QD) tunable on-chip electrostatic discharge (ESD) protection mechanism and structures. Experiments validated the programmable ESD protection concept. Prototype structures achieved an adjustable ESD triggering voltage range of 2.5V, very fast ESD response of ~100pS, ESD protection density of 25mA/μm in human body model (HBM) and 400mA/μm in charged device model (CDM), and very low leakage current of Ileak~15pA. It can be potentially used to design field-programmable ESD protection for mixed-signal IC in nano scales.

Field programmable SONOS ESD protection design

This paper reports the first SONOS-based field-programmable ESD protection concept and structure. Prototype in 130nm CMOS demonstrates wide ESD triggering tuning range of ~2V and ultra low leakage of 1.2pA. It enables post-Si on-chip/in-system ESD design programmability for complex ICs.

Design optimization of adjustable triggering dual-polarity ESD protection structures

We report design optimization of new low-triggering dual-directional SCR (LTdSCR) ESD protection structures in BiCMOS. Design optimization techniques to adjust ESD triggering voltage (V<inf>t1</inf>), as well as its impacts on ESD holding voltage (V<inf>h</inf>) and ESD protection capability, are discussed. Measurements show very low and adjustable V<inf>t1</inf>, low leakage (I<inf>leak</inf>), low noise figure (NF), low ESD-induced parasitic capacitance (C<inf>ESD</inf>) and fast ESD triggering time (t<inf>1</inf>). High ESD protection to Si ratio of ESDV∼7.49V/µm² is achieved.

A design technique overview on broadband RF ESD protection circuit designs

This paper presents an overview of the co-design technique for broadband RF ESD protection circuit designs. The unique mixed-mode ESD simulation design methodology allows full-chip design optimization and prediction of broadband RF ICs with full low-parasitic ESD protection, which were validated experimentally using ultra wideband (UWB) RF ICs and RF switch circuits in CMOS technologies.