Zoltan Nagy

A five-camera vision system for UAV visual attitude calculation and collision warning

A five-camera vision system was developed for UAV visual attitude calculation and collision warning. The vision system acquires images by using five miniature cameras, stores, and evaluates the visual data real-time with a multi-core processor system implemented in FPGA. The system was designed to be able to operate on a medium sized UAV platform, which raised numerous strict physical constraints.

A real-time multi-camera vision system for UAV collision warning and navigation

A real-time vision system with multiple cameras was developed for UAV collision warning and visual navigation for fixed-wing small- or medium-sized aircrafts. The embedded vision system simultaneously acquires images using five cameras, stores, and evaluates the visual data with an FPGA-based multi-core processor system. The system was designed to fulfill the strict size, power, and weight requirements arising from UAV on-board restrictions. The hardware parameters of the system and the performance of the algorithm are compared to the state of the art.

Analysis of myoelectric signals using a Field Programmable SoC

A platform design for the analysis of human myoelectric signals (MES) is presented. Offline recorded multichannel signals of forearm muscles are processed with a Field Programmable SoC in order to classify different movement patterns to control human-assisting electromechanical systems with multiple degrees of freedom (e.g. a prosthetic hand). Benchmark results of an ANSI C implementation are shown to assess the raw performance of the built-in ARM cores of the SoC. Possible computational bottlenecks are located based on the results and custom hardware implementations are shown to fully utilize the flexibility and performance of the used hardware platform.

FPGA-based neural probe positioning to improve spike sorting with OSort algorithm

The extracellular measurement of brain electrical activity contains local field potentials and mixtures of action potentials generated by the neurons. It is essential to determine which individual neuron produces the recorded unit activity, so spike sorting methods are used. High channel-count neural probes are capable of recording the activity of large neural ensembles from up to more than hundred individual brain positions simultaneously, pose an even greater challenge for spike sorting applied on general-purpose hardware. Real-time clinical applications could greatly benefit from a hardware-accelerated data processing, especially in the case of Field-Programmable Gate Arrays (FPGAs) or Application Specific Integrated Circuits (ASICs), which are energy-efficient compared to traditional CPUs or GPUs, and can significantly reduce the computation time required to process large amounts of high-dimensional data. In this paper, we present a real-time FPGA-based implementation of a multi-channel Online Sorting (OSort) algorithm to pre-cluster neural data. Based on this pre-processing the neurobiologists can fine-tune the position of neural probe and improve the efficiency of offline spike sorting.

Detection of single alpha-helices in large protein sequence sets using hardware acceleration

Single alpha-helices (SAHs) are increasingly recognized as important structural and functional elements of proteins. Comprehensive identification of SAH segments in large protein datasets was largely hindered by the slow speed of the most restrictive prediction tool for their identification, FT_CHARGE on common hardware. We have previously implemented an FPGA-based version of this tool allowing fast analysis of a large number of sequences. Using this implementation, we have set up of a semi-automated pipeline capable of analyzing full UniProt releases in reasonable time and compiling monthly updates of a comprehensive database of SAH segments. Releases of this database, denoted CSAHDB, is available on the CSAHserver 2 website at csahserver.itk.ppke.hu. An overview of human SAH-containing sequences combined with a literature survey suggests specific roles of SAH segments in proteins involved in RNA-based regulation processes as well as cytoskeletal proteins, a number of which is also linked to the development and function of synapses.

Acceleration of a protein structure comparison algorithm on FPGA

Proteins are among the most fundamental molecules in living organisms. Investigation and comparison of their three-dimensional structure is an important task in structural bioinformatics as global and local similarities can be of functional importance. Structure alignment and comparison is computationally intensive, so typically a number of simplifications are used for practical reasons. However, these can not always be justified on a biological or biochemical basis, and might lead to unreliable results. In this paper we describe the development and application of a method based on local structural information, suitable for comprehensive analysis of the more than 100,000 structures available today. The approach is implemented on an FPGA board allowing reasonable runtime and thus offering the possibility of parameter tuning on very large, unbiased datasets.

FPGA-based real-time multichannel neural dataset generation

Miniaturized voltage sensors (electrodes) implanted into the brain tissue are capable of recording the brief electrical impulses (spikes) of neurons located close to the electrode sites. To investigate the activity of individual neurons and discriminate spikes generated by different neurons a technique called spike sorting can be applied on the recorded data. However, the performance of current spike sorting methods is challenged by multichannel neural data recorded with high-density, highchannel count silicon probes developed recently. Our group started to develop an FPGA-based solution to accelerate the clustering of spikes detected in high-channel count neural recordings. It is a crucial step of the development to validate the performance of the clustering algorithm. This can be achieved by using ground truth datasets where the exact time of spikes fired by different single units are known. In this paper we present an FPGA-based architecture for real-time generation of multichannel hybrid ground truth datasets, which will be used for the validation of our FPGA-based clustering algorithm.

Fast evaluation of magnetic fields with multipole method implemented on FPGA

Magnetic field calculations are by far the most computationally demanding part of a micromagnetic simulation — there are significant efforts to use hardware accelerators (such as GPUs) to speed up calculations. Dedicated hardware, such as FPGAs could offer even higher performance, and flexibility / reprogrammability is usually not a requirement at this level of the computation. In this paper we present our work toward an FPGA-accelerated micromagnetic simulator code. At the hearth of the presented algorithm is an FPGA implementation of the fast multipole method in Cartesian coordinates. The algorithm promises significant performance improvements when compared to GPU-accelerated codes and will allow the simulation of large-scale spintronic or spin-wave-based devices. We will demonstrate implementation of fast multipole method using high-level hardware synthesis and benchmark the resulting hardware in terms of speed, and power consumption. We also argue that using multiple FPGAs offer a scalable solution for large-size problems.

Emulating massively parallel non-Boolean operators on FPGA

In this paper, we demonstrate an optically inspired massively parallel non-Boolean operator which can emulate 3D wave dynamics on a 2D FPGA-based architecture. The algorithm is based on the Paraxial Helmholtz Equation: which describes the beam propagation through different media with different refractive indices. To solve this wave propagation equation numerically the FPGA-accelerated hardware have to operate with spatial varying templates. The FPGA-based implementation is very well parallelizable, consequently it is also be amenable to mega-core architectures.

Cellular neural network computational scheme for efficient implementation of the FDTD method

Summaro form only given. A Cellular Neural Network (CNN) computational scheme is a processor array structure that emulates the most valuable parallelizing capabilities of the Artificial Neural Network (ANN) (L. Chua, L. Yang, Circuits and Systems, IEEE Tran, 1988). Each cell or processor inside the array has a specific processing capabilities depending on the mapped numerical application over it. This scheme has been proved in different applications that assure a PDE regular mesh mapping (A. Kiss, Z. Nagy, Journal of Circuit Theory and App, 2008).