IRC: Cross-layer design exploration of Intermittent Robust Computation units for IoTs
IIRC: Cross-layer design exploration ofIntermittent Robust Computation units for IoTs
Arman Roohi, Ronald F DeMaraElectrical and Computer Engineering Department, University of Central Florida,Orlando, FL, 32816-2362, [email protected]
Abstract —Energy-harvesting-powered computing offers in-triguing and vast opportunities to dramatically transform thelandscape of the Internet of Things (IoT) devices by utilizingambient sources of energy to achieve battery-free computing.In order to operate within the restricted energy capacity andintermittency profile, it is proposed to innovate IntermittentRobust Computation (IRC) Unit as a new duty-cycle-variablecomputing approach leveraging the non-volatility inherent inspin-based switching devices. The foundations of IRC will beadvanced from the device-level upwards, by extending a Spin HallEffect Magnetic Tunnel Junction (SHE-MTJ) device. The devicewill then be used to realize SHE-MTJ Majority/PolymorphicGate (MG/PG) logic approaches and libraries. Then a Logic-Embedded Flip-Flop (LE-FF) is developed to realize rudimentaryBoolean logic functions along with an inherent state-holdingcapability within a compact footprint. Finally, the NV-Clusteringsynthesis procedure and corresponding tool module are proposedto instantiate the LE-FF library cells within conventional RegisterTransfer Language (RTL) specifications. This selectively clusterstogether logic and NV state-holding functionality, based on en-ergy and area minimization criteria. It also realizes middleware-coherent, intermittent computation without checkpointing, micro-tasking, or software bloat and energy overheads vital to IoT.Simulation results for various benchmark circuits includingISCAS-89 validate functionality and power dissipation, area, anddelay benefits.
Index Terms —Non-volatile memory, logic-in-memory architec-ture, non-volatile flip-flop, magnetic tunnel junction (MTJ)
I. I
NTRODUCTION
For the past five decades, complementary metal-oxide-semiconductor (CMOS) has been the dominant technologyand it has provided the demanded dimension scaling forimplementing high-performance and low-power circuits. Theevolution of this charge-based CMOS devices is described andpredicted by Moore’s law [1], this prediction, that number oftransistors in integrated circuits (ICs) doubles roughly everytwo years, has continued for many years. On the other hand,by the inevitable scaling down of the feature size of theCMOS transistors which are deeper in nano-ranges, the CMOStechnology has encountered many critical challenges suchas high leakage currents, reduced gate control, high powerdensity, increased circuit noise sensitivity and high lithographycosts which obstruct the continuous dimension scaling andconsequently degrade the suitability of the CMOS technologyfor the near future high-density and energy efficient appli-cations. Explaining in more details about the first aforemen-tioned restriction, due to the quantum mechanical tunnelingof electrons from the gate electrode into the transistor channel through the gate oxide, leakage current occurs. Owing to theMoor’s law’s and mentioned problems as well as the increas-ing chip complexity, researchers have to start seeking noveltechnologies to replace the charge-based devices. Amongpromising devices, 2015 International Technology Roadmapfor Semiconductors (ITRS) [2] identifies nanomagnetic de-vices as capable post-CMOS candidates. Spintronics devicesshow promising features such as non-volatility, near-zero staticpower, and high integration density. The non-volatility meansthat the data can be maintained even if the power is off,so the standby power is reduced significantly. Moreover, dueto the possibility of 3D integration above CMOS designs atthe back-end process, distances between logic and memorycan be shortened, which reduces considerably the dynamicpower. The scalability feature of spin-based devices in additionto their low power characteristic, make the Spintronics as apromising alternative for CMOS architectures.Recently, magnetic tunnel junction (MTJ) devices are oneof the most important component of any spin-based structures,which can be configured into two different stable configu-rations. Due to the tunnel magnetoresistance (TMR) effect,these two parallel and anti-parallel states show low and highresistance, which can be denoted “0” and “1” in binary infor-mation, respectively. Two of developed switching approachesfor MTJs are spin-transfer torque (STT) [3] and spin-Halleffect (SHE) [4], in which only one bidirectional currentis required. In STT switching approach, the bidirectionalcurrent passes through an MTJ according to which it can beconfigured into P or AP state. Although STT offers severaladvantages over previous switching methods, it suffers fromsome challenges such as high write current, and switchingasymmetry [5]. Moreover, STT-MTJ is a two-terminal devicewith a shared write and read path. Consequently, undesirableswitching may occur during the read operation, and stored datacan be flipped accidentally. Recently, SHE-MTJ, a 3-terminaldevice, has been researched as a potential alternative offeringsome benefits such as decoupled read and write paths, as wellas energy efficient and high-speed write [6].
A. Research Motivation
Intermittent computation approach offers intriguing andvast opportunities to dramatically transform the landscapeof IoT devices. The Internet of Thing (IoT) devices requiredrastically-reduced energy consumption such that they areable to operate using only ambient sources of light, thermal, a r X i v : . [ c s . ET ] A p r ABLE IS
ELECTED PREVIOUS WORKS WITH SIGNIFICANT CONTRIBUTIONS TOWARDS INTERMITTENT PROCESSOR DESIGN . Approach Methodology Features Robust Element Challenges
Mementos[7] checkpointing Run-time energy estimationPeriodic system snapshots340 Byte footprint illustratedVON = 4.5V, VOFF = 2V Flash New programmingparadigms and LanguagesData movement overheadLow enduranceHibernus[8] duty-cyclingreactivehibernating Snapshot before outage76%-100% less processingtime and 49%-79% lowerenergy overhead thanMementos FerroelectricRAM (FRAM) NVMs to save all processorregister/statesNeed for sufficientenergy to save a full snapshotLong sleeping timeDINO[9] CheckpointingData versioning 582 Byte footprintillustratedAtomic tasksReduced flowcomplexity FerroelectricRAM (FRAM) Large NVM versioning infoNew programming paradigmData movement ∼ ∼ kinetic [12], and electromagnetic energy as a means to achievebattery-free computing. If lightweight embedded computingcould be realized with free and/or inexhaustible sourcesof energy, new classes of maintenance-free, compact, andinexpensive computing applications would become possible[13]. Thus, energy-harvesting-powered devices could enablea sustainable computing platform for future [14], aerospace[15], and IoT [16] applications. Energy-harvesting devicesare projected to develop towards a $2.6B market by 2024,thus automating human interaction with everyday items in ourenvironment or even life-saving medical implants within ourbodies [17].Therefore, it is proposed to research a promising classof rudimentary processing elements which utilize switchingdevices capable of leveraging (1) the restricted energy capacityand (2) the intermittent temporal energy profile, of energy har-vesting schemes. A typical energy harvesting system convertsambient energy via rectification and charge-trapping. Thenenergy is accumulated on the capacitor to generate a supplyvoltage. Once the voltage of the capacitor attains a sufficientlevel, then a lightweight embedded processing element cancommence its operation. However, the stored energy will berapidly consumed, which consequently precludes the continua-tion of execution due to an insufficient supply voltage. Hence,the supply voltage of the processor experiences intermittentbehavior. This results in an interval, τ idle , of unpredictableunavailability that can interrupt the datapath and the proces-sor clock. This charge/discharge cycle, which is an intrinsiccharacteristic of energy harvesting devices, may occur morethan hundreds of times per second for RF-based sources, and unpredictably for extended durations with kinetic and light-powered sources. Furthermore, the interval τ idle can occurirregularly and vary in duration leading us to research methodsto achieve a new Elastic Model of Computation describedherein. Hardware realization of elastic computing addressesone of the major hurdles to the propagation of energy har-vesting systems: robust operation despite discontinuities inthe ambient energy supplied from its environment. Robustintermittent operation presents a new and difficult technicalchallenge that precludes assumptions of conventional proces-sor design of the last several decades. Intermittent behaviorcan result in disturbances in the execution of programs, dataloss, glitch conditions, and lack of execution progress thatmay lead to irregular and unpredictable results [11]. Therefore,most of the existing energy harvesting systems are envisionedfor rudimentary signal detection and sensing applications suchas monitoring blood pressure or accumulating temperaturereadings. B. Advancements Beyond Previous Works
Table I lists some of the prior efforts addressing the intermit-tency challenge facing energy-harvesting-powered designs. In[7], a traditional checkpointing approach is utilized to ensurethe accurate forward progress of computation, whereby anyvolatile execution context is proactively preserved in Non-Volatile Memory (NVM) prior to anticipated periods of powerfailure. A checkpointing approach may suffer from internaland external inconsistencies after each power loss. Internalinconsistency occurs when the execution context is partially-retained in NVM, while external inconsistency arises when thepower failure occurs between two checkpoints. ig. 1. Proposed cross-layer research on spin-based designs to attain energy harvesting-powered IoT.
DINO [9] innovated a checkpointing-based approach thatutilizes non-volatile versioning to retain memory consistency,as delineated in Table I.
Duty Cycling with Scheduling [8]offers another approach for tolerating intermittence. In thismethod, critical states of the processor will be partially-retained before the power failure, then the device will enteran extremely-low power mode. However, this results in thefull availability of the device only when power interruptionis unlikely, which can incur relatively long sleeping peri-ods due to the inevitable power outages in many energyharvesting-powered systems. Chain [10] is another model forprogramming intermittent devices, in which forward-progressis ensured at the task granularity level. It utilizes idempotentprocessing concepts to make tasks restartable that never ex-perience inconsistency to keep NVM consistent. In [11], aNon-Volatile MIPS Processor (NVP) is introduced in whichspecific blocks such as register files and pipeline registerswere replaced by non-volatile elements. As listed in the lastrow of the Table I, NVP utilizes a checkpointing approachto retain the processor volatile states resulting in possibleabove-mentioned internal and external inconsistencies in non-volatile elements. Advancing beyond previous intermittentprocessors which utilize NVM resources that are distinct fromthe processing datapath, we propose a new paradigm forenergy-harvesting-powered processing, referred to as
Intermit-tent Robust Computing (IRC).II. R
ESEARCH O BJECTIVES
In this project, an Intermittent Robust Computation (IRC)Unit cross-layer approach to energy-harvesting-powered pro-cessing, from device-level to architectural-level, is developed,as shown in Figure 1. It leverages non-volatility in spin-based devices when selectively-inserted into the datapath.Simulations and analyses attain the Research Objectives (ROs)below:
RO : Construct open-source physics-based and compactmodels of novel spin-based devices designed for intermittentcomputation. Investigate spin-based device tradeoffs betweenwrite energy and volatility for various switching energy bar-riers. To explore the energy characteristics of spin-basedVLSI circuits as well as innovate novel architectural schemes,Verilog-A, Matlab, and SPICE models will be developedenabling straightforward integration with VLSI circuits inSPICE-like platforms.
RO : Design, simulate, and analyze Polymorphic Gate(PG) library and Logic-Embedded Flip-Flop (LE-FF) usingthe developed compact models to realize beyond-CMOS dat-apaths. Libraries containing a functionally-complete set ofBoolean logic gates will be defined and populated using thedeveloped device models. Moreover, the concept and designof the Logic-Embedded Flip-Flop (LE-FF) will be innovated.Extend the SHE-MTJ based design of the LE-FF from prelimi-nary results with ISCAS benchmark circuits simulated witha 40kT energy barrier, towards the LE-FF developed havingsignificantly lower energy barriers.
RO : Develop Intermittent Robust Computation IP coresrealizing normally-off computation via non-volatile datapathsusing developed PG library and LE-FF. An NV-clusteringmethodology will be developed for targeted insertion of LE-FFs as new compact means to increase the functionality ofpipeline registers. New algorithms will be developed to selec-tively utilize low energy barrier NV-PGs within the datapathto realize intermittent computation at reduced energy, whilemaintaining middleware coherence. To verify the functional-ity and demonstrate energy and performance characteristics,we implement ISCAS-89 benchmark circuits in commercialsynthesis tools.III. C
ROSS -L AYER C O -D ESIGN I MPLEMENTATION OF
IRC
A. Device-level Approach to Intermittent Computation
As shown in Figure 2, by integrating LLG Solver, Verilog-A, and SPICE models, a compact model for STT-IMTJ, STT-PMTJ [3], and SHE-MTJ [4] are developed to explore the en-ergy and delay characteristics of spin-based VLSI circuits andto innovate novel architectural schemes utilizing non-volatilelogic. They express the underlying both static and dynamicswitching behavior and encapsulate their characteristics, whileallowing straight-forward integration with VLSI circuits inSPICE-like platforms. To validate the model, several STT &SHE -based memory elements [18] and functional buildingblocks [3] are designed and their functionalities are verified.Figure 3 depicts structures of STT and SHE -MTJ along withtheir switching time.Due to the computational mechanism for spin-based de-vices, which is an accumulation-mode, spin-based devices cannaturally function as a polymorphic gate (PG) and majoritygate (MG). PGs/MGs can be cascaded to realize conjunc-tive/disjunctive Boolean gate realizations [19]. For instance,by affixing one of the three inputs in ON or OFF states, then ig. 2. Modeling and simulation process of STT/SHE MTJ devices. a 2-input OR gate or a 2-input AND gate can be realized,respectively. Therefore, we designed, simulated, and analyzedPG/MG libraries using the developed compact models. Li-braries containing a functionally-complete set of Boolean logicgates are defined and populated using the developed devicemodels.
B. Circuit-level Approach to Intermittent Computation
To achieve
RO spans the design and evaluation of Booleanlogic gates realized by the modeled non-volatile spintronicdevices. To implement a 3-input Non-Volatile PolymorphicGates (NV-PGs), which is designed using SHE-MTJ devices,a pre-charge sense amplifier (PCSA) [20] is utilized to sensethe state of the SHE-MTJs. Reference MTJ dimensions aredesigned such that its resistance value in parallel configu-ration is between low resistance, R
Low , and high resistance,R
High , of the PG cells as elaborated by following equation, R ( P − REF ) ∼ = ( R Low + R High ) / , where R Low = ( R P − P G + R HM ) / and R High = ( R AP − P G + R HM ) / . The minimumcurrent required for switching the state of the SHE-MTJdevices is called the critical current (IC), which is relativeto the dimensions of the device. In an n-input NV-PG, thedevice is designed such that at least ( n − / of the input Fig. 3. (a) two-terminal In-plane MTJ structure, (b) three-terminal SHE-MTJ, vertical and top view (left and right, respectively), and (c) magnetizationswitching time for SHE- and STT- MTJs. Fig. 4. (a)Schematic of proposed MG-based LE-FF, and, (b) circuit leveldesign of proposed 3-input SHE-based LE-FF transistors should be ON to produce a switching currentamplitude greater than the critical current. We propose toresearch approaches by which NV-PGs can be cascaded torealize conjunctive/disjunctive Boolean gate realizations. Forinstance, by affixing one (or two) of the three (or five) inputtransistors in ON or OFF states upon demand during the circuitoperation, then a 2(or 3)-input OR gate or a 2(or 3)-input ANDgate can be realized, respectively. Next, a Logic-EmbeddedFlip-Flop (LE-FF) circuit is developed [21]. It is composed ofan NV-PG based master latch using SHE-MTJ devices with30kT-35kT energy barriers achieving retention times rangingfrom hours to days, as well as a CMOS-based slave latch, asshown in Figure 4a. An LE-FF has three different functionalmodes: (1) store mode, in which a targeted Boolean logicis implemented and stored in NV-PG; (2) standby mode,in which the power is OFF and data is held in the masterlatch due to the non-volatility feature of SHE-MTJs; and (3)sense mode, where the stored data in NV-PG is read andmoved to the slave latch when the power is ON again. Ourproposed LE-FF has two interesting features in comparisonto the previously presented NV-FF designs: (a) in addition tostoring a value with near-zero standby power, similar to theother NV-FFs, the LE-FF design is capable of intrinsicallycomputing the primary Boolean expressions, resulting in area,complexity, and power reduction, (b) utilization of LE-FFs inlarge scale designs reduces their sensitive time (t S ) to powerfailures. Sensitive time is defined as the duration of signalpropagation between two NV elements including: (1) inputregisters and an NV-FF, (2) two NV-FFs, or (3) an NV-FF andoutput registers, in which if a power failure occurred, datawill be lost, and rebooting and pipeline flushing is required.The vulnerability interval is expressed by t S = t WR + t RD + t C ,where, t WR is the write operation time for the NV element,t RD is the switching time of CMOS-based slave latch, and t C is the delay of combinational circuits, the summation of allobtained sensitive times is defined as a Design Vulnerability ig. 5. Implementation methodology for RIC Unit powered by energy harvesting system.
Time (DVT), according to which smaller DVT indicates highertolerance to the power failure. The DVT of an integrated circuitcan be reduced by replacing cones of gates and NV-FFs byLE-FFs, which increases the failure robustness. In order todesign optimized NV architectures using the proposed LE-FF,we develop a systematic methodology, which incorporates allLE-FF features to design power-failure tolerant architectures.The proposed approach leverages the maximum capability ofLE-FFs in terms of replacement and implementation steps.
C. Architecture-level Approach: IRC Unit
The power profile of ambient energy sources imposesfundamental constraints on processing stability and duration.To achieve
RO , circuit-level results are extended towardsbenchmark studies corresponding to lifetime energy reductionand intermittent operational behavior demanded by IoT ap-plications. Both goals can be achieved by selectively non-volatile datapaths using low energy barrier spin-based NVdevices within the combinational circuits, as well as tar-geted insertion of LE-FFs as pipeline registers. Thus, theintermittent operation is supported without the burden ofadditional circuitry otherwise required for checkpoint-restore,backup, etc. Figure 5 shows the VLSI synthesis methodologyproposed herein for implementing logic circuits. The circuit-level simulation framework is utilized to develop a standardcell PG library containing a sufficient range of energy-efficientlogic gates, as well as LE-FF circuits. We develop an NV-clustering methodology, which takes a Hardware DescriptionLanguage (HDL) representation of a datapath and PG-basedgate modules as its inputs and produces an optimized NV-enhanced datapath. A preliminary version of this algorithm isdeveloped in Python, which explores the HDL of the logiccircuit and finds the gates and pipeline registers that can becombined and replaced by spin-based LE-FF circuits, and theremainder of pipeline registers will be replaced by NV-FFs. Inparticular, the algorithm first finds all of the FFs in the design,and then checks the cone of logic gates connected to the inputsof the FFs. If each cone of gates meets the circuit-level criteriamentioned below, then the cone and its corresponding FF canbe replaced by an LE-FF circuit. The three primary criteriaare: (1) it should be possible to implement the cone of gateswith a single PG, (2) fan-out of every gate in the cone shouldnot exceed one, (3) none of the gates in the cone should beconnected to the output of another FF [21]. To exemplify the functionality of the proposed methodology,the s27 circuit from the ISCAS-89 benchmark is analyzed,as shown in Figure 6a. To estimate area, power, and delayimprovements of our proposed approach, we have utilized acommercial synthesis tool, i.e. Synopsys Design Compiler, tomap the input HDL to the developed spin-based PG library.The estimated results for 12 ISCAS-89 benchmark circuits areshown in Figure 7. Our proposed approach has achieved anaverage of 15%, 22%, 14%, and 33% improvements in termsof area, power, delay, and energy consumption, respectively,compared to the conventional intermittent computing circuitswhere all of the pipeline registers are replaced with NV-FFs.These estimated results are obtained by using SHE-MTJs with40 kT energy barrier ( ∆ ), which can provide non-volatility foryears. However, in the energy-harvesting-powered IoT devices,retention time in order of days and hours could be sufficientto achieve proper functionality. Therefore, the energy barrierof SHE-MTJ devices can be reduced to 30kT, realizing 25%reduction in switching critical current ( I C ∝ ∆ ) and approxi-mately 44% decrease in energy consumption ( E ∝ P ∝ I ),while providing non-volatility for a few hours. Combining theabove energy reductions to achieve at least 60% improvementsin energy consumption while reducing circuit lifetime energy-delay-product by at least 70% compared to existing designsof comparable area motivates the proposed effort.IV. C ONCLUSION AND F UTURE W ORK
In this project, the primary NV-clustering methodology wasextended to realize the targeted insertion of 40-35kT SHE-MTJdevices within the combinational logic, enabling gate-levelpipelining that is essential for energy harvesting applications.Next steps as future work, to avoid energy overhead causedby power gating control signals, we will create multiple gatingdomains including clustered gates, which can be simulta-neously power-gated during circuit operation. Moreover, thestate-holding characteristic of the spin-based devices facilitatesultra-fine-grained pipelining of logic paths without incurringadditional overheads, which previously existed in conventionalCMOS-based designs due to the presence of pipeline registers.Thus, we will research the benefit to operate intermittentlywithout backing-up the processor state to separate non-volatilestorage. Optimizations will be applied to improve energy andperformance profiles of utilizing micro-benchmarks from atransportable suite of IoT benchmarks which will be devel- ig. 6. (a) s27 schematic with highlighted FFs, and (b) all three applied NV-Clustering scheme.Fig. 7. (a) s27 schematic with highlighted FFs, and (b) all three appliedNV-Clustering scheme. oped. Finally, we will determine the minimum amount ofthe NV-PGs, which are required to be used in combinationalcircuits to ensure glitch-free PG-based IP Cores supportingintermittent computation with reduced energy consumption.The research insights gained regarding PG insertion will begeneralized to arbitrary combinational logic expressions suchas multi-modal Finite Impulse Response (FIR) filters with abackup power saving mode, which are representative casestudies for IoT applications powered by energy harvestingapplications. R
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