PCM-trace: Scalable Synaptic Eligibility Traces with Resistivity Drift of Phase-Change Materials
Yigit Demirag, Filippo Moro, Thomas Dalgaty, Gabriele Navarro, Charlotte Frenkel, Giacomo Indiveri, Elisa Vianello, Melika Payvand
aa r X i v : . [ c s . ET ] F e b PCM-trace: Scalable Synaptic Eligibility Traceswith Resistivity Drift of Phase-Change Materials
Yi˘git Demira ˘g , Filippo Moro , Thomas Dalgaty , Gabriele Navarro , Charlotte Frenkel , Giacomo Indiveri ,Elisa Vianello , and Melika Payvand Institute of Neuroinformatics, University of Zurich and ETH Zurich, Switzerland CEA-Leti, Grenoble, France , CEA-List, Nano-INNOV, Universit´e Paris-Saclay, France
Abstract —Dedicated hardware implementations of spikingneural networks that combine the advantages of mixed-signalneuromorphic circuits with those of emerging memory technolo-gies have the potential of enabling ultra-low power pervasivesensory processing. To endow these systems with additionalflexibility and the ability to learn to solve specific tasks, it isimportant to develop appropriate on-chip learning mechanisms.Recently, a new class of three-factor spike-based learning ruleshave been proposed that can solve the temporal credit assignmentproblem and approximate the error back-propagation algorithmon complex tasks. However, the efficient implementation of theserules on hybrid CMOS/memristive architectures is still an openchallenge. Here we present a new neuromorphic building block,called PCM-trace, which exploits the drift behavior of phase-change materials to implement long lasting eligibility traces, acritical ingredient of three-factor learning rules. We demonstratehow the proposed approach improves the area efficiency by > × compared to existing solutions and demonstrates a techno-logically plausible learning algorithm supported by experimentaldata from device measurements. I. I
NTRODUCTION
Neuromorphic engineering uses electronic analog circuitelements to implement compact and energy-efficient intelligentcognitive systems [1]–[4]. Leveraging substrate’s physics toemulate biophysical dynamics is a strong incentive towardultra-low power and real-time implementations of neuralnetworks using mixed-signal memristive event-based neuro-morphic circuits [5]–[8]. The majority of these systems arecurrently deployed in edge-computing applications only in inference mode , in which the network parameters are fixed.However, learning in edge computing can have many advan-tages, as it enables adaptation to changing input statistics,reduced network congestion, and increased privacy. Indeed,there have been multiple efforts implementing Spike-TimingDependent Plasticity (STDP)-variants and Hebbian learningusing neuromorphic processors [9]–[11]. These methods con-trol Long Term Depression (LTD) or Long Term Potentiation(LTP) by specific local features of pre- and post-synapticactivities. However, local learning rules themselves do notprovide any guarantee that network performance will improvein multi-layer or recurrent networks. Local error-driven ap-proaches, e.g., the Delta Rule, aim to solve this problem butfail to assign credit for neurons that are multiple synapsesaway from the network output [12], [13]. On the other hand,it has been recently shown that by using external third-factor neuromodulatory signals (e.g., reward or predictionerror in reinforcement learning, teaching signal in supervisedlearning), this can be achieved in hierarchical networks [14], [15]. However, there needs to be a mechanism for synapsesto remember their past activities for long periods of time,until the reward event or teacher signal is presented. In thebrain, these signals are believed to be implemented by calciumions, or CAMKII enzymes in the synaptic spine [16] andare called eligibility traces. In machine learning, algorithmictop-down analysis of the gradient descent demonstrated howlocal eligibility traces at synapses allow networks to reachperformances comparable to error back-propagation algorithmon complex tasks [17]–[19]. Examples of neuromorphic plat-forms that implement these types of eligibility traces in spikingneural networks already exist [20]–[22]. However, learningin these platforms is only supported through the use ofvon-Neumann processors, either shared with the computationof network dynamics [21] or a dedicated core [20], [22].Relying on numerical integration, these platforms do notleverage the physics of their computing substrate and are notfree from the von-Neumann bottleneck problem [23], [24].On the other hand, mixed-signal analog/digital neuromorphiccircuits allow the use of in-memory computing that directlyemulates the desired neural and synaptic dynamics using thephysics of analog elements [25]–[27]. However, even thoughprogress has been made in extending the duration of synaptictraces using advanced Fully-Depleted Silicon on Insulator(FDSOI) technologies [28], implementing tens-of-seconds-long time constants solely based on Complementary Metal-Oxide-Semiconductor (CMOS) is not scalable, as it requiresthe use of large capacitors. In this paper, we present a novel ap-proach to exploit the drift behavior of Phase Change Memory(PCM) devices to intrinsically perform Eligibility Trace (ET)computation over behavioral timescales. We present the
PCM-trace building block as a hybrid memristive-CMOS circuitsolution that can lead to record-low area requirements persynapse. To the best of our knowledge, this is the first workthat uses a memristive device not only to store the weightof synapses, but also to keep track of synaptic eligibility tointeract with a third factor toward scalable next-generation on-chip learning. II. E
LIGIBILITY T RACES
The ET can be described as a decaying synaptic variable asin Eq. (1). The value of the ET at the synapse between pre-synaptic neuron j and post-synaptic neuron i can be controlledas a usually linear function, f j , of the pre-synaptic activity x j , and potentially non-linear function g i of the post-synapticactivity x i such that e t +∆ tij = αe tij + ηf j ( x tj ) g i ( x ti ) , (1) R e s i s t a n ce ( Ω ) × ExperimentModel
100 ns V RESET
Fig. 1: Experimental (dots), and simulated (dashed lines)resistance drift characteristics at constant room temperature.where η is a constant and α = e − ∆ t/τ m is the decay rate of ET, τ m is decay time-constant up to tens of seconds in behaviouraltime-scales and ∆ t is discrete time-step [14]. The e ij acts as atemporal correlation detector between pre-synaptic f j ( x j ) andpost-synaptic g i ( x i ) functions. The instantaneous correlationbetween f j and g i is defined as synaptic tagging , which isaccumulated by e ij to keep track of past correlations. The f and g functions are determined by the chosen synapticlearning rule. For example, f j ( x j ) is the low-pass filtered pre-synaptic events in e-prop and BDSP [17], [29], and g i ( x i ) isa non-linear function of the post-synaptic state for e-prop andSuperSpike [18].III. PCM M EASUREMENTS
Temporal evolution of electrical resistivity is a widely-observed phenomenon in PCM due to the rearrangementsof atoms in the amorphous phase [30]. This behavior iscommonly referred to as structural relaxation or drift. Tostart the drift, a strong RESET pulse is applied to inducea crystalline to amorphous phase transition where the PCMis melted and quenched. The low-ordered and highly-stressedamorphous state then evolves to a more energetically favorableglass state within tens of seconds [31].At constant ambient temperature, the resistivity follows R ( t ) = R ( t ) (cid:18) tt (cid:19) ν , (2)where R ( t ) is the resistance measured at time t and ν isthe drift coefficient. It has been experimentally verified bymany groups that Eq. (2) can successfully capture the driftdynamics [31]–[33], from microseconds to hours range [34].We integrated Ge Sb Te -based PCM in state-of-the-artPCM heater-based devices fabricated in the Back-End-Of-Line(BEOL) based on
130 nm
CMOS technology. The PCM thick-ness is
50 nm with the bottom size of
60 nm ×
60 nm . Driftmeasurements were performed on three devices to monitorthe temporal evolution of the resistance in the High-ResistiveState (HRS) state, particularly confirming the model in Eq. (2).The test was conducted by first resetting all the cells byapplying a RESET pulse to the heater, which has a width of
100 ns with rising and falling times, and a peak voltageof .
85 V . Then, an additional programming pulse is used tobring the devices to different initial conditions, corresponding C ondu c t a n ce ( µ S ) Synaptic taggingAccumulating e-trace2 4 6 8 10 12Time (s) Higher Baseline
Fig. 2: Accumulating ET using PCM-trace drift model (Eq. 3).After resetting the PCM-trace device at t = 0 , 5 randomsynaptic tags are applied to the synapse, implemented by agradual SET for each tag that results in increase in theconductivity. The device can keep the ET for more than
10 s .to R ( t = 1 s) = [1 .
77 MΩ , .
39 MΩ , .
89 MΩ] . The low-fielddevice resistances are measured every for
30 s by applyinga READ pulse which has the same timing of the RESET pulsebut a peak voltage of .
05 V .IV. PCM-
TRACE
PCM-trace is a novel method to implement seconds-longET for the synapse using the drift feature of PCM. Bywriting Eq. (2) as a difference equation of the conductance,we can show that the temporal evolution of the conduc-tance has decay characteristics similar to Eq. (1) such that G t +∆ tij = ( t − t p t − t p +∆ t ) ν G tij , where G t ij = 1 /R t ij , and t p isthe last programming time as drift re-initializes with everygradual SET [35], [36]. The main difference is that the rate ofchange in PCM resistivity is a function of time; nevertheless,its time constant is comparable for behavioral time-scales as τ P CM = − ∆ t/log (( t/ ( t + ∆ t )) ν ) is on the order of tens ofseconds [37]. Therefore, the PCM-trace dynamics can emulatethe ET of the synapse as follows: G t +∆ tij = (cid:18) t − t p t − t p + ∆ t (cid:19) ν G tij + ηf j ( x tj ) g i ( x ti ) (3)In the PCM-trace method (Eq. 3), the accumulating termon the ET is implemented by applying a gradual SET to thePCM device whenever the synapse is tagged. To maximize thenumber of accumulations a PCM device can handle withoutgetting stuck in the Low-Resistive State (LRS) regime, someoperational conditions need to be satisfied. We initialize thedevice to HRS by applying a strong RESET pulse, and waitfor an initialization time t init of at least
250 ms for thedevice resistance to increase. If t init is too short, the deviceconductance would still be too high to be able to accumulateenough tags; and if it is too long, the decay will be weaker(see Eq. 2). Initialization time can be modulated to reach thedesired drift speed depending on the material choice and theapplication. After the initialization time, whenever the synapseis tagged, a single gradual SET (with an amplitude of µ A and a pulse width of
100 ns with rising and falling times)is applied. To make sure that the device stays in the HRS, aread-verify-set scheme can be used. Finally, the value of theET can be measured after seconds by reading the conductanceof the device (see Fig. 2). r e s y n a p t i c neu r o n P o s t s y n a p t i c neu r o nS y n a p s e S y n a p t i c e f fi c a cy S y n a p t i c e li g i b ili t y t r a c e j i N p a r a ll e l m e m r i s t o r d e v i c e s i Fig. 3: Multi PCM-trace concept. Each synapse has a weightand a PCM-trace block where multiple parallel PCM deviceskeep the ET of the synapse with their natural drift behavior.The postsynaptic neuron receives the sum of product of thepre-synaptic activity and the weight block. In parallel, thePCM-trace block calculates the ET as a function of pre- andpost-synaptic activities (Eq. 3), to be used in the weight update.
A. Multi PCM-trace
The number of gradual SET pulses applied to a single PCM-trace device is limited, because each pulse partially increasesthe device conductivity and eventually move the device towardits LRS ( < ), where the drift converges to a higherbaseline level. This problem can be solved by storing thesynaptic ET distributed across multiple PCM devices, as inFig. 3. By successively routing the tags to multiple PCMdevices, the number of gradual SET pulses to be applied persingle device is significantly reduced. Fig. 4 demonstrates theincrease of effective dynamic range (number of updates to ETwithout getting stuck in the LRS) using multiple PCM devices. PCM ijij
102 20 3001.20.251.20.251.20.2512103
Time (s) G ( µ s ) G ( µ s ) G ( µ s ) G ( µ s ) G ( µ s ) r d -f r d -f d e l a y i n it t a g s PCM ij W ij Fig. 4: Accumulating ET using multi-PCM configuration.Synapse receives 15 tags between
300 ms to whichare routed to three different devices shown in the top threeplots. The effective ET is calculated by applying a READpulse to the parallel PCM devices. The initialization durationand synaptic activity period are shown with dashed lines in thebottom plot. The synaptic efficacy W ij is modified dependingon the state of ET once the third-factor signal arrives. P R OG R E AD PREREW UP /DN V PROG
NEURON+LB e W e W e W e UP /DN NEURON+LB
Fig. 5: PCM-trace-based neuromorphic architecture for three-factor learning. Only positive ET ( e + ij ) and W + ij are shown.V. C IRCUIT AND A RCHITECTURE
A. PCM-trace Architecture
An example in-memory event-based neuromorphic architec-ture is shown in Fig. 5, where the PCM-trace is employed toenable three-factor learning on behavioral time scales.
Synapse:
Each synapse includes a weight block W ij inwhich two PCM devices are used in differential configurationto represent positive and negative weights [38]. The effectivesynaptic weight is calculated as the difference of these twoconductance values, i.e., W ij = W + ij − W − ij . Also, eachsynapse has a PCM-trace block e ij that keeps the ET. Insidethe PCM-trace block, there are two PCM devices, keepingtrack of the positive and negative correlation between pre andpost-synaptic neurons. On the onset of the pre-synaptic inputspike, P RE j , (i) W ij is read, and the current is integrated bythe post-synaptic neuron i ; (ii) Based on the U P / DN signalfrom the learning block (LB), a gradual SET programmingcurrent is applied to positive/negative PCM-trace devices. Neuron with Learning Block (LB):
The LB estimates thepre-post synaptic neuron correlation using the Spike DrivenSynaptic Plasticity (SDSP) rule [39]. At the time of thepre-synaptic spike, the post-synaptic membrane variable iscompared against a threshold, above (below) which an
U P ( DN ) signal is generated representing the tag type. On thearrival of the third factor binary reward signal, REW , thestate of the ETs devices is read by the V P ROG block (Fig. 6b)which generates a gate voltage that modulates the current thatprograms the weight devices W ij (see Alg. 1). B. Circuit simulation
Fig. 6 describes the block diagram of the LB implementingSDSP rule, which calculates the pre-post neurons’ correlation.The membrane variable (described here as a current I mem since circuits are in current-mode) is compared against athreshold value I th through a Bump circuit [38], [40]. Theoutput of this block is digitized through a current comparator(in our design chosen as a Winner-Take-All (WTA) block [41])and generates U P / DN signals if the membrane variable isabove/below the threshold I th , and STOP, SP , if they areclose within the dead zone of the bump circuit [40]. Fig. 6bpresents the circuit schematic which reads the PCM-trace andgenerates V P ROG . To read the state of the device, a voltage lgorithm 1:
Three-factor learning with PCM-trace W + ij = rand (); W − ij = rand () ; RESET ( e + ij ); RESET ( e − ij ) ; while t < taskDuration do I i,x = 1 − ( V i,th − V i,mem ) /V i,th ; if @Pre and t > t init then forall e ij doif I i,x > I + th then GRADUAL SET ( e + ij ) ; if I i,x < I − th then GRADUAL SET ( e − ij ) ; if Reward thenforall W ij do I ij,e + , I ij,e − = READ ( e + ij , e − ij ) ; I + P ROG = I ij,e + ∗ scale const ; I − P ROG = I ij,e − ∗ scale const ; GRADUAL SET ( W + ij , I + P ROG ) ; GRADUAL SET ( W − ij , I − P ROG ) ;divider is formed between the PCM device and a pseudoresistor, highlighted in green. As the device resistance changes,the input voltage to the differential pair, highlighted in red,changes. This change is amplified by the gain of the diff. pairand the device current is normalized to its tail current givingrise to I P ROG which develops V P ROG through the diode-connected NMOS transistor. V P ROG is connected to the gateof the transistor in series with the weight PCM (see Fig. 5).Fig. 7a plots PRE, I mem , the output of the learning block atthe time of the PRE, and the gradual SET pulse applied tothe device. As shown, the U P signal is asserted when themembrane current is higher than the threshold indicated inred, which causes a gradual SET pulse with µ A to beapplied across the PCM-trace device upon PRE events. Fig 7bshows the generated I P ROG as a function of the state of theET device. The higher the ET device’s resistance, the lessthe accumulated correlation, thus the lower the programmingcurrent that should be applied to the weight device. Theresistance on the x axis of the plot matches the measuredresistance of PCM devices shown in Fig. 1.VI. D
ISCUSSION AND C ONCLUSION
Long-lasting ETs enable the construction of powerful learn-ing mechanisms for solving complex tasks by bridging thesynaptic and behavioral time-scales. In this paper, for the firstTABLE I: Area comparison of ET implementation
Area ( µ m ) τ (s) Area/ τ ( µ m s − )CMOS [28] ×
17 6 56 . PCM [This work] × > < . BUMP
Correlation Detector I mem I th UPSPDN
WTA
CurrentComparator
Learning Block I ET (a) (b) V PROG I PROG
Fig. 6: (a) Learning block diagram generating UP/DN signalsas a function of the correlation between pre and post-synapticactivity. (b) V P ROG circuit reading from the ET device throughthe voltage divider (green) and generating I P ROG through thediff. pair (red) to program the weight device.
560 580 600Time (ms)050100 C u rr e n t( µ A ) I SET
PRE C u rr e n t( n A ) I mem I + th PRE & UP M Ω)0 . . . . . . I P R O G ( m A ) Fig. 7: a) From the top: PRE events, POST membrane current( I mem ) and learning threshold ( I th ), PRE events only when I mem is higher than I th , and corresponding gradual SETcurrent pulse applied to PCM-trace. b) Programming currentto be applied to the weight PCM as a function of ET state.time, we proposed to use the drift of PCM devices to imple-ment ETs, and analyzed their feasibility for implementation inexisting fabrication technologies.The implementation of the three-factor learning rules withETs per synapse requires complex memory structures for keep-ing track of the ET and the weight. Our proposed approachhas clear advantages for scaling. Table I shows a comparisonbetween our PCM synapse and a CMOS-only implementationin
22 nm
FDSOI technology from [28].PCM is among the most advanced emerging memory tech-nology integrated into the neuromorphic domain [42]. Ourapproach of using PCM to store both the synaptic weight andthe ET requires no additional nano-fabrication methods.A
CKNOWLEDGMENT
This project has received funding from the EuropeanUnion’s H2020 research and innovation programme under theMarie Skłodowska-Curie grant agreement No 861153, H2020MeM-Scales project (871371) and ERA-NET CHIST-ERAprogramme by SNSF (20CH21186999 / 1).
EFERENCES[1] C. Mead, “How we created neuromorphic engineering,”
Nature Elec-tronics , vol. 3, no. 7, pp. 434–435, 2020.[2] E. Chicca, F. Stefanini, C. Bartolozzi, and G. Indiveri, “Neuromorphicelectronic circuits for building autonomous cognitive systems,”
Proceed-ings of the IEEE , vol. 102, no. 9, pp. 1367–1388, 9 2014.[3] G. Indiveri and T. Horiuchi, “Frontiers in neuromorphic engineering,”
Frontiers in Neuroscience , vol. 5, no. 118, pp. 1–2, 2011.[4] C. Mead, “Neuromorphic electronic systems,”
Proceedings of the IEEE ,vol. 78, no. 10, pp. 1629–36, 1990.[5] E. Chicca and G. Indiveri, “A recipe for creating ideal hybridmemristive-CMOS neuromorphic processing systems,”
Applied PhysicsLetters , vol. 116, no. 12, p. 120501, 2020.[6] A. Serb, J. Bill, A. Khiat, R. Berdan, R. Legenstein, and T. Prodromakis,“Unsupervised learning in probabilistic neural networks with multi-statemetal-oxide memristive synapses,”
Nature communications , vol. 7, p.12611, 2016.[7] Y. Li, Z. Wang, R. Midya, Q. Xia, and J. J. Yang, “Review of memristordevices in neuromorphic computing: materials sciences and devicechallenges,”
Journal of Physics D: Applied Physics , vol. 51, no. 50,p. 503002, 2018.[8] S. Spiga, A. Sebastian, D. Querlioz, and B. Rajendran, “Role of resistivememory devices in brain-inspired computing,” in
Memristive Devicesfor Brain-Inspired Computing , ser. Woodhead Publishing Series inElectronic and Optical Materials, S. Spiga, A. Sebastian, D. Querlioz,and B. Rajendran, Eds. Woodhead Publishing, 2020, pp. 3–16.[9] N. Qiao, H. Mostafa, F. Corradi, M. Osswald, F. Stefanini, D. Sum-islawska, and G. Indiveri, “A reconfigurable on-line learning spikingneuromorphic processor comprising 256 neurons and 128k synapses,”
Frontiers in neuroscience , vol. 9, p. 141, 2015.[10] C. Frenkel, M. Lefebvre, J.-D. Legat, and D. Bol, “A 0.086-mm2 12.7-pj/SOP 64k-synapse 256-neuron online-learning digital spiking neuro-morphic processor in 28-nm CMOS,”
IEEE Transactions on BiomedicalCircuits and Systems , vol. 13, no. 1, pp. 145–158, 2019.[11] M. Payvand and G. Indiveri, “Spike-based plasticity circuits for always-on on-line learning in neuromorphic systems,” in . IEEE, 2019, pp.1–5.[12] B. Widrow and M. Hoff, “Adaptive Switching Circuits,”in ∼ {} widrow/papers/c1960adaptiveswitching.pdf[13] M. Payvand, Y. Demirag, T. Dalgaty, E. Vianello, and G. Indiveri,“Analog weight updates with compliance current modulation of binaryrerams for on-chip learning,” in . IEEE, 2020, pp. 1–5.[14] W. Gerstner, M. Lehmann, V. Liakoni et al. , “Eligibility traces andplasticity on behavioral time scales: experimental support of neohebbianthree-factor learning rules,” Front. Neur. Circ. , vol. 12, p. 53, 2018.[15] E. O. Neftci, “Data and power efficient intelligence with neuromorphiclearning machines,” iScience , vol. 5, pp. 52–68, 2018.[16] M. Sanhueza and J. Lisman, “The camkii/nmdar complex as a molecularmemory,”
Molecular brain , vol. 6, no. 1, pp. 1–8, 2013.[17] G. Bellec, F. Scherr, A. Subramoney, E. Hajek, D. Salaj, R. Legenstein,and W. Maass, “A solution to the learning dilemma for recurrentnetworks of spiking neurons,” bioRxiv , p. 738385, 2020.[18] F. Zenke and S. Ganguli, “Superspike: Supervised learning in multilayerspiking neural networks,”
Neural computation , vol. 30, no. 6, pp. 1514–1541, 2018.[19] D. E. Rumelhart, G. E. Hintont, and R. J. Williams, “Learning repre-sentations by back-propagating errors,”
Nature , vol. 323, no. 6088, pp.533–536, 1986.[20] M. Davies, N. Srinivasa, T.-H. Lin, G. Chinya, Y. Cao, S. H. Choday,G. Dimou, P. Joshi, N. Imam, S. Jain et al. , “Loihi: A neuromorphicmanycore processor with on-chip learning,”
IEEE Micro , vol. 38, no. 1,pp. 82–99, 2018.[21] S. Furber, F. Galluppi, S. Temple, and L. Plana, “The SpiNNakerproject,”
Proceedings of the IEEE , vol. 102, no. 5, pp. 652–665, May2014.[22] A. Gr¨ubl, S. Billaudelle, B. Cramer, V. Karasenko, and J. Schemmel,“Verification and design methods for the brainscales neuromorphichardware system,” arXiv preprint arXiv:2003.11455 , 2020. [23] J. Backus, “Can programming be liberated from the von Neumannstyle?: a functional style and its algebra of programs,”
Communicationsof the ACM , vol. 21, no. 8, pp. 613–641, 1978. [Online]. Available:http://doi.acm.org/10.1145/359576.359579[24] G. Indiveri and S.-C. Liu, “Memory and information processing inneuromorphic systems,”
Proceedings of the IEEE , vol. 103, no. 8, pp.1379–1397, 2015.[25] N. Qiao, C. Bartolozzi, and G. Indiveri, “An ultralow leakage synapticscaling homeostatic plasticity circuit with configurable time scales up to100 ks,”
IEEE Transactions on Biomedical Circuits and Systems , 2017.[26] C. Bartolozzi and G. Indiveri, “Synaptic dynamics in analog VLSI,”
Neural Computation , vol. 19, no. 10, pp. 2581–2603, Oct 2007.[27] M. Payvand, M. E. Fouda, F. Kurdahi, A. Eltawil, and E. O. Neftci,“Error-triggered three-factor learning dynamics for crossbar arrays,”in . IEEE, 2020, pp. 218–222.[28] A. Rubino, M. Payvand, and G. Indiveri, “Ultra-low power silicon neu-ron circuit for extreme-edge neuromorphic intelligence,” in
InternationalConference on Electronics, Circuits, and Systems, (ICECS), 2019 , 112019, pp. 458–461.[29] A. Payeur, J. Guerguiev, F. Zenke, B. A. Richards, and R. Naud, “Burst-dependent synaptic plasticity can coordinate learning in hierarchicalcircuits,” bioRxiv , 2020.[30] D. Ielmini, S. Lavizzari, D. Sharma, and A. L. Lacaita, “Temperatureacceleration of structural relaxation in amorphous ge2sb2te5,”
AppliedPhysics Letters , vol. 92, no. 19, p. 193511, 2008.[31] M. Le Gallo, D. Krebs, F. Zipoli, M. Salinga, and A. Sebastian, “Collec-tive structural relaxation in phase-change memory devices,”
AdvancedElectronic Materials , vol. 4, no. 9, p. 1700627, 2018.[32] I. Karpov, M. Mitra, D. Kau, G. Spadini, Y. Kryukov, and V. Karpov,“Fundamental drift of parameters in chalcogenide phase change mem-ory,”
Journal of Applied Physics , vol. 102, no. 12, p. 124503, 2007.[33] A. Pirovano, A. L. Lacaita, F. Pellizzer, S. A. Kostylev, A. Benvenuti,and R. Bez, “Low-field amorphous state resistance and threshold voltagedrift in chalcogenide materials,”
IEEE Transactions on Electron Devices ,vol. 51, no. 5, pp. 714–719, 2004.[34] S. Kim, B. Lee, M. Asheghi, F. Hurkx, J. P. Reifenberg, K. E. Goodson,and H.-S. P. Wong, “Resistance and threshold switching voltage driftbehavior in phase-change memory and their temperature dependence atmicrosecond time scales studied using a micro-thermal stage,”
IEEETransactions on Electron Devices , vol. 58, no. 3, pp. 584–592, 2011.[35] Y. Demirag, “Multiphysics modeling of Ge2Sb2Te5 based synapticdevices for brain inspired computing,” Master’s thesis, Ihsan DogramaciBilkent University, Ankara, Turkey, Jul. 2018.[36] S. Nandakumar, M. Le Gallo, I. Boybat, B. Rajendran, A. Sebastian,and E. Eleftheriou, “A phase-change memory model for neuromorphiccomputing,”
Journal of Applied Physics , vol. 124, no. 15, p. 152135,2018.[37] M. P. Lehmann, H. A. Xu, V. Liakoni, M. H. Herzog, W. Gerstner, andK. Preuschoff, “One-shot learning and behavioral eligibility traces insequential decision making,”
Elife , vol. 8, p. e47463, 2019.[38] M. Payvand, M. V. Nair, L. K. M¨uller, and G. Indiveri, “A neuromorphicsystems approach to in-memory computing with non-ideal memristivedevices: From mitigation to exploitation,”
Faraday Discussions , vol. 213,pp. 487–510, 2019.[39] J. M. Brader, W. Senn, and S. Fusi, “Learning real-world stimuliin a neural network with spike-driven synaptic dynamics,”
NeuralComputation , vol. 19, no. 11, pp. 2881–2912, 2007.[40] T. Delbrueck and C. Mead, “Bump circuits,” in
Proceedings of Interna-tional Joint Conference on Neural Networks , vol. 1, 1993, pp. 475–479.[41] S.-C. Liu, J. Kramer, G. Indiveri, T. Delbruck, and R. Douglas,
AnalogVLSI:Circuits and Principles . MIT Press, 2002.[42] I. Boybat, M. L. Gallo, T. Moraitis, T. Parnell, T. Tuma, B. Rajendran,Y. Leblebici, A. Sebastian, E. Eleftheriou et al. , “Neuromorphic com-puting with multi-memristive synapses,”