A. Castillo Atoche

Experiment design regularization-based hardware/software codesign for real-time enhanced imaging in uncertain remote sensing environment

A new aggregated Hardware/Software (HW/SW) codesign approach to optimization of the digital signal processing techniques for enhanced imaging with real-world uncertain remote sensing (RS) data based on the concept of descriptive experiment design regularization (DEDR) is addressed. We consider the applications of the developed approach to typical single-look synthetic aperture radar (SAR) imaging systems operating in the real-world uncertain RS scenarios. The software design is aimed at the algorithmic-level decrease of the computational load of the large-scale SAR image enhancement tasks. The innovative algorithmic idea is to incorporate into the DEDR-optimized fixed-point iterative reconstruction/enhancement procedure the convex convergence enforcement regularization via constructing the proper multilevel projections onto convex sets (POCS) in the solution domain. The hardware design is performed via systolic array computing based on a Xilinx Field Programmable Gate Array (FPGA) XC4VSX35-10ff668 and is aimed at implementing the unified DEDR-POCS image enhancement/reconstruction procedures in a computationally efficient multi-level parallel fashion that meets the (near) real-time image processing requirements. Finally, we comment on the simulation results indicative of the significantly increased performance efficiency both in resolution enhancement and in computational complexity reduction metrics gained with the proposed aggregated HW/SW co-design approach.

An efficient Gaussian random number architecture for MIMO channel emulators

Gaussian random numbers (GRN) generators are indispensable components in channel emulators for producing multiplicative and additive noises. Efficient designs of these GRN generators are required for testing the newest communications standards, which consider multiple channels working at higher data rates. In this paper, a new reconfigurable architecture for the generation of GRN at each clock cycle is proposed. The design consists in the polynomial approximation of the inverse method, implemented through parallel computing techniques using processor arrays. Time and area analysis carried out show a performance improvement when compared with previous works. Finally, the architectures statistical performance was corroborated in QAM-VBLAST transmission scheme.

Laboratory Projects for Engineering Students with FPGA

This paper proposes a series of related laboratory projects to the image processing area through reconfigurable integrated circuits like FPGA (field programmable gate array). With the implementation of these projects, the students will not only develop skills in electronic design, they also will increase their knowledge as engineers, with the integration of electronic engineering and computer science in the design of reconfigurable hardware with FPGAs. The algorithms proposed in these laboratory projects, for the image processing, are coded in C++ and are implemented in the embedded microcontroller Microblaze.

An improved hardware design for matrix inverse based on systolic array QR decomposition and piecewise polynomial approximation

Reconstructive signal processing algorithms involve complex computations, where matrix inversion is one of the most complex operations required by several signal processing applications (e.g., image processing or MIMO systems in wireless communication transmission). Currently, QR decomposition implemented with systolic arrays have been proposed in recent studies; however, the internal structure of the boundary cell requires complex operations such as square root and its reciprocal. The challenge of this paper consist in the improvement of a hardware architecture for matrix inversion. This improvement is achieved using systolic arrays and polynomial approximation techniques. Particularly, the inverse square root operation and its reciprocal are efficiently implemented with a piecewise polynomial approximation architecture in a systolic array structure achieving significant gains in area and time performance.

High-speed low-power parallel Random Number Generator for wireless channel emulators

Uniform Random Number Generators (URNG) are an indispensable block in channel emulators systems. They are required for producing noises and distortions for testing wireless communication systems. Therefore, there is a necessity of producing several uncorrelated URNG. This paper presents a high-speed, low-power URNG generator for producing parallel uncorrelated data flows, based on the use of the hybrid cellular automatas (CA) method. Time and area analysis carried out, showing that the proposed architecture can be used in parallel to test multiple-input multiple output (MIMO) systems. Statistical analyses are presented corroborating its quality. In addition, the proposed architecture has been implemented in a VLSI device, showing its potentially massive use in commercial channel emulators.

An efficient systolic array grid-based structure of the robust Bayesian regularization technique for real-time enhanced imaging in uncertain remote sensing environment

Abstract In this paper, we address a hardware implementation of the efficient robust Bayesian regularization architecture for the real-time enhancement of large-scale remote sensing (RS) imaging. The efficient sense of the proposed architecture is related to the high-performance embedded implementation that is achieved with the aggregation of parallel computing and systolic array design techniques in a novel grid connected-based accelerator. Then, the developed high-speed accelerator is integrated with an embedded processor via the HW/SW co-design paradigm. The presented approach is used for solving RS image enhancement/reconstruction of the ill-conditioned inverse spatial spectrum pattern estimation problems via an interesting low-cost high-performance embedded computing solution. Finally, we show the achieved results and how we drastically reduced the computational load for real-world large-scale geospatial images.In this paper, we address a hardware implementation of the efficient robust Bayesian regularization architecture for the real-time enhancement of large-scale remote sensing (RS) imaging. The efficient sense of the proposed architecture is related to the high-performance embedded implementation that is achieved with the aggregation of parallel computing and systolic array design techniques in a novel grid connected-based accelerator. Then, the developed high-speed accelerator is integrated with an embedded processor via the HW/SW co-design paradigm. The presented approach is used for solving RS image enhancement/reconstruction of the ill-conditioned inverse spatial spectrum pattern estimation problems via an interesting low-cost high-performance embedded computing solution. Finally, we show the achieved results and how we drastically reduced the computational load for real-world large-scale geospatial images.

A case study of OpenCL-based parallel programming for low-power remote sensing applications

With the advent of high-performance embedded computing (HPEC) systems, many digital processing algorithms are now implemented by special-purpose massively parallel processors. In this paper, a low-power ARM/GPU co-design architecture is addressed using OpenCL-based parallel programming for implementing complex reconstructive signal processing operations. Such operations are accelerated using data-parallel functions on the GPU and ARM processor, in a HW/SW co-design scheme via OpenCL API calls. Experimental results shows the achieved computational performance and the effectiveness of the OpenCL standard comparing the framework against traditional parallel embedded versions.

A Fading Channel Simulator Implementation Based on GPU Computing Techniques

Channel simulators are powerful tools that permit performance tests of the individual parts of a wireless communication system. This is relevant when new communication algorithms are tested, because it allows us to determine if they fulfill the communications standard requirements. One of these tests consists of evaluating the system performance when a communication channel is considered. In this sense, it is possible to model the channel as an FIR filter with time-varying random coefficients. If the number of coefficients is increased, then a better approach to real scenarios can be achieved; however, in that case, the computational complexity is increased. In order to address this issue, a design methodology for computing the time-varying coefficients of the fading channel simulators using consumer-designed graphic processing units (GPUs) is proposed. With the use of GPUs and the proposed methodology, it is possible for nonspecialized users in parallel computing to accelerate their simulation developments when compared to conventional software. Implementation results show that the proposed approach allows the easy generation of communication channels while reducing the processing time. Finally, GPU-based implementation takes precedence when compared with the CPU-based implementation, due to the scattered nature of the channel.

Aggregation of parallel computing and hardware/software co-design techniques for high-performance remote sensing applications

Developing computationally efficient processing techniques for massive volumes of hyperspectral data is critical for space-based Earth science and planetary exploration. In particular, many remote sensing imaging applications require a response in real time in areas such as environmental modeling and assessment, target detection for military and homeland defense/security purposes, and risk prevention and response. This paper propose the aggregation of parallel computing and HW/SW co-design techniques using processor arrays (PAs) units as specialized hardware architectures for the real time enhancement of remote sensing imagery. An extended descriptive experiment design regularization (DEDR) method that incorporates projections onto convex solution sets (POCS) for spatial spectrum pattern (SSP) reconstruction is used to be efficiently implemented (i.e., HW-level) via the new proposition of the aggregation techniques. Finally, it is reported and discussed the Xilinx Virtex-5 FPGA implementation and high-performance issues related to real time enhancement of large-scale real-world RS imagery.

A Triply Selective MIMO Channel Simulator Using GPUs

A methodology for implementing a triply selective multiple-input multiple-output MIMO simulator based on graphics processing units GPUs is presented. The resulting simulator is based on the implementation of multiple double-selective single-input single-output SISO channel generators, where the multiple inputs and the multiple received signals have been transformed in order to supply the corresponding space correlation of the channel under consideration. A direct consequence of this approach is the flexibility provided, which allows different propagation statistics to each SISO channel to be specified and thus more complex environments to be replicated. It is shown that under some specific constraints, the statistics of the triply selective MIMO simulator are the same as those reported in the state of art. Simulation results show the computational time improvement achieved, up to 650-fold for an 8 × 8 MIMO channel simulator when compared with sequential implementations. In addition to the computational improvement, the proposed simulator offers flexibility for testing a variety of scenarios in vehicle-to-vehicle V2V and vehicle-to-infrastructure V2I systems.