J. Vázquez Castillo

An efficient Gaussian random number architecture for MIMO channel emulators

Gaussian random numbers (GRN) generators are indispensable components in channel emulators for producing multiplicative and additive noises. Efficient designs of these GRN generators are required for testing the newest communications standards, which consider multiple channels working at higher data rates. In this paper, a new reconfigurable architecture for the generation of GRN at each clock cycle is proposed. The design consists in the polynomial approximation of the inverse method, implemented through parallel computing techniques using processor arrays. Time and area analysis carried out show a performance improvement when compared with previous works. Finally, the architectures statistical performance was corroborated in QAM-VBLAST transmission scheme.

Laboratory Projects for Engineering Students with FPGA

This paper proposes a series of related laboratory projects to the image processing area through reconfigurable integrated circuits like FPGA (field programmable gate array). With the implementation of these projects, the students will not only develop skills in electronic design, they also will increase their knowledge as engineers, with the integration of electronic engineering and computer science in the design of reconfigurable hardware with FPGAs. The algorithms proposed in these laboratory projects, for the image processing, are coded in C++ and are implemented in the embedded microcontroller Microblaze.

An accurate hardware sum-of-cisoids fading channel simulator for isotropic and non-isotropic mobile radio environments

The rapid technological development in the field of wireless communications calls for devices capable of reproducing and simulating the behavior of the channel under realistic propagation conditions. This paper presents a hardware fading channel simulator that is able to generate stochastic processes characterized by symmetrical and asymmetrical Doppler power spectral densities (PSDs) depending on the assumption of isotropic or non-isotropic scattering. The concept of the proposed hardware simulator is based on an implementation of the sum-of-cisoids (SOC) method. The hardware simulator is capable of handling any configuration of the cisoids amplitudes, frequencies, and phases. Each of the cisoids that constitutes the SOC model is implemented using a piecewise polynomial approximation technique. The investigation of the higher-order statistics of the generated fading processes, like the level-crossing rate (LCR) and the average duration of fades (ADF), shows that our design is able to reproduce accurately the key features of realistic channel models that are considered as candidates for the latest wireless communication standards.

A New Tool for Intelligent Parallel Processing of Radar/SAR Remotely Sensed Imagery

A novel parallel tool for large-scale image enhancement/reconstruction and postprocessing of radar/SAR sensor systems is addressed. The proposed parallel tool performs the following intelligent processing steps: image formation, for the application of different system-level effects of image degradation with a particular remote sensing (RS) system and simulation of random noising effects, enhancement/reconstruction by employing nonparametric robust high-resolution techniques, and image postprocessing using the fuzzy anisotropic diffusion technique which incorporates a better edge-preserving noise removal effect and faster diffusion process. This innovative tool allows the processing of high-resolution images provided with different radar/SAR sensor systems as required by RS endusers for environmental monitoring, risk prevention, and resource management. To verify the performance implementation of the proposed parallel framework, the processing steps are developed and specifically tested on graphic processing units (GPU), achieving considerable speedups compared to the serial version of the same techniques implemented in C language.

High-speed low-power parallel Random Number Generator for wireless channel emulators

Uniform Random Number Generators (URNG) are an indispensable block in channel emulators systems. They are required for producing noises and distortions for testing wireless communication systems. Therefore, there is a necessity of producing several uncorrelated URNG. This paper presents a high-speed, low-power URNG generator for producing parallel uncorrelated data flows, based on the use of the hybrid cellular automatas (CA) method. Time and area analysis carried out, showing that the proposed architecture can be used in parallel to test multiple-input multiple output (MIMO) systems. Statistical analyses are presented corroborating its quality. In addition, the proposed architecture has been implemented in a VLSI device, showing its potentially massive use in commercial channel emulators.

Arbitrary Distribution Random Variable Generator for Channel Emulators

Channel emulation is a fundamental part in designing, testing and validation of wireless communication systems. It brings the possibility of modeling certain channel characteristics without the necessity of performing field tests. In standards, channel models are specified in terms of several power spectral distributions that require the generation of random variables with predefined statistics. However, current emulator approaches consider different generators for each specific distribution. In this work it is presented an efficient hardware architecture for arbitrary random variable generation that can be used for all the distributions of a wireless channel emulator. The proposed architecture is based on the inversion method implemented via piecewise polynomial approximation. The architecture was validated under the WiMAX standardas the parameters generator of the channels temporal variations. Implementation results show that this single module can produce all random parameters for current communication standards.

A Fading Channel Simulator Implementation Based on GPU Computing Techniques

Channel simulators are powerful tools that permit performance tests of the individual parts of a wireless communication system. This is relevant when new communication algorithms are tested, because it allows us to determine if they fulfill the communications standard requirements. One of these tests consists of evaluating the system performance when a communication channel is considered. In this sense, it is possible to model the channel as an FIR filter with time-varying random coefficients. If the number of coefficients is increased, then a better approach to real scenarios can be achieved; however, in that case, the computational complexity is increased. In order to address this issue, a design methodology for computing the time-varying coefficients of the fading channel simulators using consumer-designed graphic processing units (GPUs) is proposed. With the use of GPUs and the proposed methodology, it is possible for nonspecialized users in parallel computing to accelerate their simulation developments when compared to conventional software. Implementation results show that the proposed approach allows the easy generation of communication channels while reducing the processing time. Finally, GPU-based implementation takes precedence when compared with the CPU-based implementation, due to the scattered nature of the channel.

High-Speed Stochastic Processes Generator Based on Sum-of-Sinusoids for Channel Emulation

In this paper a high-speed fading architecture that generates multiple stochastic processes based on the Sum-of-Sinusoids (SOS) method is presented. In the proposed architecture, the fading samples are generated according to either symmetrical or asymmetrical power spectral density (PSD) in an efficient FPGA-based architecture. This proposal allows the emulation of more realistic channels in non-isotropic environments. The sinusoid evaluation is performed by the piecewise polynomial approximation using processor arrays (PAs) technique in an efficient hardware-level structure. This technique offers the maximum possible parallelism, high accuracy in the generated samples, high frequency resolution as well as high rate sinusoid evaluation. The proposed architecture can be used to construct a flexible channel emulator for the current communication standards.