A. Christou

Pt and PtSix Schottky contacts on n‐type β‐SiC

Schottky barrier rectifying contacts using e‐beam‐deposited platinum have been demonstrated on n‐type β‐SiC. The electrical properties of these contacts were examined as a function of annealing temperature using I‐V and C‐V measurements. Auger analysis was used to study the metallurgical reactions at the Pt/SiC interface. Short annealing cycles in the 350–800 °C temperature range led to formation of a mixed structure of PtSix and PtC at the interface, evidenced by migration of platinum into the SiC above 350 °C. The barrier height was found to increase from 0.95 to 1.35 eV with increasing annealing temperature. The rectifying characteristics improved following an initial 350 °C anneal and remained relatively stable up to 800 °C.

Silicide formation and interdiffusion effects in Si-Ta, SiO2-Ta AND Si-PtSi-Ta thin film structures

The formation of TaSi2 in the Si-PtSi-Ta and Si-Ta systems has been studied using Auger spectroscopy, x-ray diffraction and electron diffraction techniques. The reaction of tantalum with PtSi was observed by Sinha, et al.l to take place with high temperature (800°-900°c) annealing of thin film systems consisting of Si-PtSi-Ta-W1. In the present investigation, it is shown that tantalum reacts with PtSi at approximately 600°C to form a mixture of Ta5Si3 and TaSi2 and predominantly TaSi2 at 785°C. Platinum is displaced at the refractory metal (Ta)-PtSi interface, whereupon the more stable refractory metal-silicide is formed. The displaced platinum reacts further with the excess silicon which diffuses from the Si-PtSi interface. The Si-PtSi-Ta reaction is similar to the Si-PtSi-W reaction. However, unlike tungsten which migrates very little in the Si-PtSi-W system, tantalum appears to interdiffuse with the PtSi at temperatures as low as 600°C. In the case of the Si-Ta couple, TaSi2 forms at approximately 750°C as determined by transmission electron microscopy (TEM) measurements. The kinetics of TaSi2 formation at the Si-Ta interface are compared to that which takes place at the PtSi-Ta interface to determine the influence of the PtSi layer. Silicide formation was not observed in SiO2-Ta specimens. after anneals up to 800°c. At 750°C Ta2O5 formed as observed by electron diffraction.

Smooth and continuous Ohmic contacts to GaAs using epitaxial Ge films

Ohmic contacts to n‐type GaAs have been developed using epitaxial Ge films on GaAs alloyed with Ni overlayers by solid‐state diffusion at temperatures of 450–550 °C. The contacts are smooth and continuous, showing no evidence of phase separation or other surface structure. Interdiffusion at the Ge‐GaAs and Ni/Ge‐GaAs interfaces was examined by Auger electron spectroscopy (AES) sputter profiling techniques. An abrupt profile is observed at both the as‐deposited and sintered Ge‐GaAs interface. With the presence of a Ni overlayer, significant interdiffusion between Ge and GaAs is revealed by AES profiles. These results, together with the current‐voltage (I‐V) characteristics of similar contacts prepared on p‐type GaAs, indicate the presence of a Ge‐doped n+ layer at the Ni/Ge‐GaAs interface.

Surface treatment of (11̄02) sapphire and (100) silicon for molecular beam epitaxial growth

A low‐temperature surface preparation technique for molecular beam epitaxial growth of silicon on sapphire and silicon is described. Thermal desorption of regrown oxide has been accomplished at 850 °C and epitaxial growth at 650 °C. A comparison of two surface treatment techniques for silicon (100) and sapphire (1102) substrates is reported.

Amorphous thin film diffusion barriers on GaAs and InP

Abstract Thin films amorphous WSi and TiWSi diffusion barriers have been studied on GaAs and InP surfaces for the purpose of establishing their reliability for ohmic contacts and Schottky barriers, particularly under high temperature stress. The amorphous films were formed by a new method in which alternate layers of tungsten or TiW and silicon were sputter deposited to a total thickness of about 1300 A and subsequently annealed near the glass transition temperature Tg(≈500°C). Electron channeling and reflection electron diffraction were used to determine the amorphous nature of the films as deposited and after 4 h anneals near Tg. The as-deposited films had interfacial amorphous regions with compositions determined by interfacial reactions during the sputtering process. As-deposited WSi films showed a weak channeling pattern which came from the unreacted polycrystalline tungsten layers. From Auger electron spectroscopy (AES) sputter profiles, it was concluded that the amorphous regions were at the WSi interfaces which had the required tungsten-to-silicon composition ratio. After annealing at 500 °C for 4 h, the films were completely amorphous with no marked evidence of crystallization, indicating interfacial reactions extended completely into the tungsten layers. High magnification scanning electron microscopy (by a factor of 20 000) examination of the films after annealing revealed smooth and continuous surfaces with no evidence of grain boundaries. Diffusion along grain boundaries between gold and GaAs or InP in these amorphous thin films was thus almost completely eliminated. Interdiffusion of gold in layered structures (e.g. Au/(WSi)/GaAs) was studied by AES sputter profiling techniques. No interdiffusion of gold or GaAs was observed after 16 h anneals at 400 °C. With Au/(WSi)/InP structures, no interdiffusion was observed after 8 h anneals at 450 °C. These results are significant improvements over those for previous polycrystalline diffusion barriers (e.g. TiPt) which degrade after 1 h at 350 °C. Based on the AES sputter profiles, the diffusion coefficients in WSi amorphous thin films were found to be less than 3 × 10−18 cm2 s−1 at 400 °C for gold, gallium and arsenic and less than 6 × 10−18 cm2s−1 at 450 °C for gold, indium and phosphorus.

Photoreflectance measurement of strain in epitaxial GaAs on silicon

The valence‐band splitting due to strain in molecular‐beam epitaxially grown GaAs on Si has been observed by photoreflectance. The strain has been obtained from the valence‐band splitting and was found to be in agreement with results obtained by x‐ray rocking curve measurements, photoluminescence, and Raman spectroscopy. The temperature dependence of the strain has also been measured and found to be in agreement with thermal expansion effects.

Failure Mechanism Study of GaAs MODFET Devices and Integrated Circuits

GaAs Modulation Doped Field Effect Transistor (MOD-FET) integrated circuits have been accelerated stress tested under bias at 150°C, 200°C, 210°C. The failure mode has been identified to be a diffusion controlled degradation of the 2 DEC layers. Alpha particle irradiation resulted in a decrease in charge collection efficiency, and catastrophic gate burnout.

Formation of epitaxial Si1−xGex films produced by wet oxidation of amorphous SiGe layers deposited on Si(100)

Epitaxial SiGe/Si structures have been formed by wet oxidation of amorphous SiGe films. Amorphous, 1000‐A‐thick Si0.86Ge0.14 films were electron beam evaporated onto RCA cleaned Si(100) substrates at a background pressure of 1×10−7 Torr. They were then wet oxidized in an open tube furnace, at 900 °C for various times. They have been examined by reflective high‐energy electron diffraction and Rutherford backscattering. Results indicate the formation of an epitaxial SiGe layer following the oxidation, whereas a polycrystalline layer forms following a vacuum or nitrogen ambient anneal. It is suggested that the oxide contamination at the amorphous SiGe/Si interface is too high to allow solid phase epitaxial growth to occur in an oxygen‐free ambient, but during the oxidation process, some native oxide is dissolved due to a gradient of silicon from the substrate to the growing SiO2 on the surface. This allows grains of the SiGe alloy to orient with respect to the substrate, and secondary grain growth occurs dur...

High Power Pulse Reliability of GaAs Power FETs

A study was made of degradation and burnout of GaAs power FETs resulting from high power RF pulses on the gate while operating at X-band. Burnout power per unit gate width (W/mm) was found to be an important parameter. The failure mechanisms were found to be subsurface burnout and high-field induced metal bridging from the gate to the source or drain. Numerical simulations show high current density transients at the gate and hot electron thermal transients at the source and drain. Hot electrons are created near the edges of the gate and at the source and drain regions by a high power pulse. It is suggested that these lead to degradation by recoil-enhanced interdiffusion at the gate and thermally-induced metal-GaAs interdiffusion, mainly at the source and drain. If such degradation progresses to the point where filamentary metal-GaAs interdiffusions reach the substrate/active channel interface, subsurface burnout is initiated by thermal runaway.

A mechanism for radiation‐induced degradation in GaAs field‐effect transistors

GaAs field‐effect transistors (FETs) exposed to 40 α/sec for about 60 sec in the gate region revealed burnout from under the gate to both the drain and source. To explain this result, we show by using a 2D numerical FET simulation that a single event, particularly normal to the gate, has all the harmful electrical and thermal transients as that of a reverse gate‐voltage pulse or positive drain‐voltage pulse. The latter two are well known to initiate burnout failure mechanisms in GaAs FETs, depending on duty cycle and peak power applied. The onset of burnout due to a succeeding single event may be further aided by the ionization‐enhanced outdiffusion of deep‐level traps to the active channel during a series of single events. The experimental data, principally from SEM analysis and degradation of I‐V characteristics, seem to support the thermal runaway burnout mechanism proposed in this paper. Other mechanisms previously suggested are either ruled out or deemed inadequate. A high‐fluence radiation‐hardened ...