A. G. O’Neill

Formation and role of graphite and nickel silicide in nickel based ohmic contacts to n-type silicon carbide

Nickel-based contacts, deposited on 4H-SiC C-face substrates, were annealed at temperatures ranging from 800to1040°C and the phase composition of the contact layers analyzed by x-ray diffraction techniques. Ni2Si was identified as the dominant phase for annealing temperatures exceeding 925°C, with further increases in concentration with increasing temperature. At the highest annealing temperature of 1040°C, a 40nm thick nanocrystalline graphite film at the Ni2Si–SiC interface was discovered and its presence confirmed by Raman spectroscopy. The roles of the Ni2Si and graphite films in the formation of ohmic contacts were determined by their subsequent exclusion from the contact composition. Following deposition and annealing, the Ni2Si and graphite layers were etched away selectively and replaced with new metal films deposited at room temperature and without any annealing. Measurement of the current-voltage characteristics revealed that the ohmic nature of the contacts was preserved after removal of the Ni...

Study of strain relaxation in Si/SiGe metal-oxide-semiconductor field-effect transistors

We report a study of strained Si metal-oxide-semiconductor field-effect transistors (MOSFET’s) fabricated using a high thermal budget. The impact of Si channel strain on MOSFET performance, leakage current, and yield is investigated for Si1−xGex virtual substrates having Ge compositions varying from 0% to 30%. Increasing the Ge fraction in the SiGe virtual substrate increases the amount of tensile strain in the Si layer and consequently increases the electron mobility. High levels of strain, however, reduce the critical thickness of strained Si, above which Si becomes metastable and susceptible to relaxation during high-temperature device fabrication. Increasing the Ge composition in the virtual substrate up to 30% is shown to result in significant enhancements in MOSFET drain current and transconductance due to increased strain in the device channels. However, cross-wafer electrical yield data as a function of Ge composition are reported and show that increasing Ge compositions above 15% simultaneously r...

Effect of metal–oxide–semiconductor processing on the surface roughness of strained Si/SiGe material

The impact of metal–oxide–semiconductor processing on strained Si/SiGe device structures has been examined. Material was grown by gas-source molecular beam epitaxy and ultra low pressure chemical vapor deposition, with different as-grown surface roughness. The effects of RCA cleaning, gate oxidation and rapid thermal annealing on this material were studied by atomic force microscopy (AFM) and optical profilometry. Certain processes caused reactions common to both material types, whereas others yielded dissimilar responses. Filtering AFM roughness data of specific wavelengths enabled the effects of processing on large-scale surface roughness dominated by the cross-hatching morphology and smaller scale microroughness to be investigated. The results suggest that as-grown Si/SiGe material quality is not a good indicator of processed device performance, rather morphological changes which occur during processing must be considered.

Effect of post-implantation anneal on the electrical characteristics of Ni 4H-SiC Schottky barrier diodes terminated using self-aligned argon ion implantation

Abstract The effects of post-implantation annealing on the electrical characteristics of Ni 4H-SiC Schottky barrier diodes terminated using self-aligned Ar+ ion implantation have been investigated. Results show that the Ar+ edge termination may be modelled as a shunt linear resistive path at low to moderate reverse bias levels and at low forward bias levels. Low temperature (400–700°C) annealing is shown to increase the equivalent resistance of the edge termination by two orders of magnitude without significant effect on the breakdown voltage. Annealing temperatures above 600°C are, however, shown to degrade the on-state performance. A breakdown voltage of 1530 V was achieved on the implanted and annealed samples, representing 90% of the theoretical parallel plane breakdown voltage. Temperature dependent measurements, made over the temperature range 25–400°C show that the equivalent resistance of the edge termination is thermally activated with an exponential temperature coefficient of −0.02 K−1. Behaviour at moderate forward bias levels is typical of thermionic emission whilst operation at high forward bias is dominated by a linear series resistance which shows a quadratic temperature dependence, increasing by a factor of 6 over the range 25–400°C.

Impact of virtual substrate growth on high performance strained Si/SiGe double quantum well metal-oxide-semiconductor field-effect transistors

Strained Si/SiGe n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) have been fabricated using a dual quantum well structure. The heterostructure is designed for maximum performance from both n- and p-channel devices using a single Si0.85Ge0.15 virtual substrate. An optimized thermal budget has been used for device fabrication, which was possible due to the strain-compensated layer structure providing increased material robustness to strain relaxation. Epitaxial growth has been carried out by low-pressure chemical vapor deposition (LPCVD) at two different temperatures. Strained Si MOSFETs fabricated on virtual substrates grown at high temperature exhibited drain current enhancements three times as large as those demonstrated by strained Si MOSFETs fabricated on material grown at low temperature, compared with control Si devices. Detailed material analysis suggests that the higher degree of surface roughness and higher defect density of the low temperature LPCVD material limits the perf...

Impact of virtual substrate quality on performance enhancements in strained Si/SiGe heterojunction n-channel MOSFETs

Abstract The performance of surface channel MOSFET devices is dependent on the Si/SiO 2 interface roughness. This paper examines the performance demonstrated by strained Si/SiGe heterojunction n-channel MOSFET devices (HNMOSFETs) fabricated on ultra-low pressure CVD (ULPCVD) material compared with unstrained Si control devices. The surface channel HNMOSFETs were found to exhibit performance enhancements in terms of transconductance of approximately 135% compared with their Si counterparts. In addition, the electrical characteristics of the HNMOSFETs displayed increased uniformity and improvements in the peak transconductance in excess of 75% compared with equivalent devices fabricated on strained Si/SiGe GS-MBE material. Atomic force microscopy and transmission electron microscopy showed that the favourable characteristics of the ULPCVD strained Si/SiGe devices are due to reduced cross-hatch severity of the ULPCVD material, which is shown to decrease nanoscale roughness at the Si/SiO 2 interface.

Extraction of strained-Si metal-oxide-semiconductor field-effect transistor parameters using small signal channel conductance method

Channel conductance has been employed to extract several important parameters such as threshold voltage, gain, effective channel length, series resistance, and mobility for strained-Si metal-oxide-semiconductor field-effect-transistors fabricated on relaxed silicon-germanium virtual substrates with Ge composition up to 25%. Analytical models have been developed by taking into account the effect of strain (i.e., Ge composition) on these parameters. The low field mobility of the devices has been found to increase linearly up to a Ge composition of 25% in the virtual substrate. A modified channel conductance technique has been used to extract critical fields accurately. This has also been used to predict the dependence of mobility on electric field in a strained-Si device. The critical field for silicon devices has been found to be 65kVcm−1, while for strained-Si devices, it has been found to decrease from 62.5 to 30kVcm−1 with increasing Ge composition (15% to 25%) in the virtual substrate. The reported res...

Quantum-mechanical modeling of current-voltage characteristics of Ti-silicided Schottky diodes

Based on the interfacial-layer and quantum-mechanical (QM) carrier transport approach, a theoretical model is proposed to predict the anomalous behavior of low-temperature current-voltage (I-V) characteristics of Ti-silicided Schottky diodes. Physical parameters such as barrier height, ideality factor, series resistance, and effective Richardson constant of silicided Schottky diodes are extracted from the forward experimental I-V characteristics. Simulations of both the forward and reverse I-V characteristics have also been performed using extracted parameters. Results are compared with the models, such as, thermionic-emission-diffusion and thermionic-emission with barrier lowering reported in the literature. It is shown that for Ti-silicided Schottky diodes, the use of QM transport model provides a better agreement with the experimental data.

Optimisation of a power 4H-SiC SIT device for RF heating applications

Abstract In this paper, the optimisation procedure for a static induction transistor (SIT) in silicon carbide is described and its application in a typical RF heating circuit is presented. A field plate edge termination is optimised for a 10 μm thick epitaxial layer with doping in the range 10 15 cm −3 to 10 16 cm −3 . Results show a breakdown voltage of 1280 V, corresponding to 68% of the theoretical value. For the chosen application an epitaxial layer doping level of 5×10 15 cm −3 is revealed to offer the best compromise. This allows pinch off of drain voltages exceeding 600 V from a 20 V gate drive whilst achieving a current density of 250 A cm −2 at an on-state voltage of less than 1 V. Transient simulations are performed for a series load resonant converter with a switching frequency of 27.12 MHz. The results emphasise the suitability of the device for RF heating applications.

The effects of grain boundary diffusion anisotropy on via electromigration failure

Electromigration performance of multilevel interconnect vias is investigated using a three-dimensional computer model. The model uses the finite-element method to obtain self-consistently the temperature and current density distributions in order to calculate electromigration fluxes. The model includes the polycrystalline grain structure of the tracks as well as stress-migration and concentration gradient backfluxes. While in single level systems, failure can be analyzed with two-dimensional models because the fluxes are homogeneous, the inclusion of the third dimension along the track thickness is necessary for multilevel systems. In addition to the effects of hot spots, current crowding, and microstructure, it is found that the anisotropy of the grain boundary diffusion plays an important role in determining the locations of void formation. The microstructural details of the track at the interface with the via, including grain boundary geometry, are very important for electromigration studies.