Luke Driscoll

A model for capacitance reconstruction from measured lossy MOS capacitance-voltage characteristics

A capacitance model is developed and a correction formula is derived to reconstruct the intrinsic oxide capacitance value from measured capacitance and conductance of lossy MOS devices. Due to discrepancies during processing, such as cleaning, an unwanted lossy dielectric layer is present in the oxide/semiconductor interface causing the measured capacitance in strong accumulation to be frequency dependent. The capacitance–voltage characteristics after correction are free from any frequency dispersion effect and give the actual oxide thickness in accumulation at all frequencies. Simulation of the measured capacitance–frequency curve was carried out using the model. The model was applied to SiO2/Si, SiO2/strained Si and GaO2/GaAs MOS capacitors.

Study of strain relaxation in Si/SiGe metal-oxide-semiconductor field-effect transistors

We report a study of strained Si metal-oxide-semiconductor field-effect transistors (MOSFET’s) fabricated using a high thermal budget. The impact of Si channel strain on MOSFET performance, leakage current, and yield is investigated for Si1−xGex virtual substrates having Ge compositions varying from 0% to 30%. Increasing the Ge fraction in the SiGe virtual substrate increases the amount of tensile strain in the Si layer and consequently increases the electron mobility. High levels of strain, however, reduce the critical thickness of strained Si, above which Si becomes metastable and susceptible to relaxation during high-temperature device fabrication. Increasing the Ge composition in the virtual substrate up to 30% is shown to result in significant enhancements in MOSFET drain current and transconductance due to increased strain in the device channels. However, cross-wafer electrical yield data as a function of Ge composition are reported and show that increasing Ge compositions above 15% simultaneously r...

Study of single- and dual-channel designs for high-performance strained-Si-SiGe n-MOSFETs

Results comparing strained-Si-SiGe n-channel MOSFET performance of single-and dual-surface channel devices fabricated using 15% Ge content SiGe virtual substrates are presented. Device fabrication used high thermal budget processes and virtual substrates were not polished. Mobility enhancement factors exceeding 1.6 are demonstrated for both single-and dual-channel device architectures compared with bulk-Si control devices. Single-channel devices exhibit improved gate oxide quality, and larger mobility enhancements, at higher vertical effective fields compared with the dual-channel strain-compensated devices. The compromised performance enhancements of the dual-channel devices are attributed to greater interface roughness and increased Ge diffusion resulting from the Si/sub 0.7/Ge/sub 0.3/ buried channel layer.

C–V characterization of strained Si/SiGe multiple heterojunction capacitors as a tool for heterojunction MOSFET channel design

Capacitance–voltage (C–V) characteristics are used to investigate double heterojunction strained Si/SiGe MOS capacitors. Structures of this type potentially form the channels of CMOS devices based on the strained Si/SiGe material system. The technique represents a fast and non-destructive method to determine important characteristics such as layer thicknesses, threshold voltages and band offsets. Moreover, it contributes to the design of optimum heterostructures for CMOS. Experimental C–V data are compared with simulation and complementary results including SIMS and TEM to confirm the accuracy of the technique.

Optimization of alloy composition for high-performance strained-Si-SiGeN-channel MOSFETs

On-state and off-state performance of strained-Si-SiGe n-channel MOSFETs have been investigated as a function of SiGe virtual substrate alloy composition. Performance gains in terms of on-state drain current and maximum transconductance of up to 220% are demonstrated for strained-Si-SiGe devices compared with Si controls. Device performance is found to peak using a virtual substrate composition of Si/sub 0.75/Ge/sub 0.25/. MOSFET fabrication used high thermal budget processing and good gate oxide quality has been maintained for virtual substrates having Ge compositions up to 30%. Off-state characteristics are found to be more sensitive to strain relaxation than on-state characteristics.

Impact of virtual substrate growth on high performance strained Si/SiGe double quantum well metal-oxide-semiconductor field-effect transistors

Strained Si/SiGe n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) have been fabricated using a dual quantum well structure. The heterostructure is designed for maximum performance from both n- and p-channel devices using a single Si0.85Ge0.15 virtual substrate. An optimized thermal budget has been used for device fabrication, which was possible due to the strain-compensated layer structure providing increased material robustness to strain relaxation. Epitaxial growth has been carried out by low-pressure chemical vapor deposition (LPCVD) at two different temperatures. Strained Si MOSFETs fabricated on virtual substrates grown at high temperature exhibited drain current enhancements three times as large as those demonstrated by strained Si MOSFETs fabricated on material grown at low temperature, compared with control Si devices. Detailed material analysis suggests that the higher degree of surface roughness and higher defect density of the low temperature LPCVD material limits the perf...

Evaluation of strained Si/SiGe material for high performance CMOS

The enhanced electrical performance of dual quantum well strained Si/SiGe n-channel MOSFETs has been investigated as a function of SiGe material quality. The higher electron mobility in strained Si compared with bulk Si has been translated into performance gains in terms of device transconductance and on-state drain current exceeding 120% compared with simultaneously fabricated Si controls. Increased performance was demonstrated for a wide range of gate lengths and operating conditions. Trade-offs between optimum device design and SiGe material quality have been investigated. The greatest performance enhancements are achieved through device fabrication on SiGe virtual substrate material grown by low-pressure chemical vapour deposition (LPCVD) at high temperature. Improved surface morphology, defect density and gate oxide quality are found to be the dominating factors in the enhanced performance of the devices compared with strained Si/SiGe MOSFETs fabricated on LPCVD material grown at low temperature. However, even degraded SiGe material arising from low temperature LPCVD growth resulted in strained Si/SiGe n-channel MOSFETs exhibiting significant improvements in device operation compared with conventional Si MOSFETs. The performance advantages offered by strained Si/SiGe devices fabricated on material grown at both low and high temperatures exceed that of a typical Si CMOS technology generation.

Extraction of strained-Si metal-oxide-semiconductor field-effect transistor parameters using small signal channel conductance method

Channel conductance has been employed to extract several important parameters such as threshold voltage, gain, effective channel length, series resistance, and mobility for strained-Si metal-oxide-semiconductor field-effect-transistors fabricated on relaxed silicon-germanium virtual substrates with Ge composition up to 25%. Analytical models have been developed by taking into account the effect of strain (i.e., Ge composition) on these parameters. The low field mobility of the devices has been found to increase linearly up to a Ge composition of 25% in the virtual substrate. A modified channel conductance technique has been used to extract critical fields accurately. This has also been used to predict the dependence of mobility on electric field in a strained-Si device. The critical field for silicon devices has been found to be 65kVcm−1, while for strained-Si devices, it has been found to decrease from 62.5 to 30kVcm−1 with increasing Ge composition (15% to 25%) in the virtual substrate. The reported res...

N-MOSFET performance in single and dual channel strained Si/SiGe CMOS architectures

The performance of single and dual channel strained Si n-MOSFETs fabricated using CMOS process. A TEM image of the strained Si/gate oxide interface was examined. Capacitance-voltage measurement on MOS capacitor was investigated. The gate oxide interface trap density as a function of band gap energy for MOS capacitor fabricated on the single and dual channel architectures was illustrated. Field effect mobility was investigated as a function of vertical effective field on MOSFETs having 10 /spl mu/m gate lengths and 5 /spl mu/m gate widths.

High Performance Strained Si/SiGe N-channel MOSFETs: Impact of Alloy Composition and Layer Architecture

Single and dual n-channel strained Si MOSFETs, fabricated by the same high thermal budget process, are compared for the first time. Si1-xGex virtual substrates, having 0.1 < x < 0.3, are used to compare off-state and on-state device performance. Transconductances and current drive up to 240% higher than control Si MOSFETs are demonstrated. Electron mobility is found to peak using a virtual substrate composition of Si0.75Ge0.25. 1. Intr oduction Growth of strained Si on SiGe virtual substrates is known to improve carrier mobility and so increase MOSFET current and transconductance. Theoretical studies have suggested that the optimum performance of strained Si/SiGe MOSFETs is achieved by the use of a strained Si surface electron channel and a buried hole channel of compressively strained SiGe [1]. As virtual substrate Ge composition increases, strain relaxation during high temperature MOSFET processing may degrade overall device performance and it is unclear what impact Ge diffusion will have on device operation, particularly if a compressively strained SiGe channel of high Ge composition is used. 2. Device Design and Fabrication Strained Si n-channel MOSFETs were fabricated on relaxed Si1-xGe x virtual substrates (VS) with x = 0.10, 0.15, 0.20, 0.25 and 0.30. The rms surface roughness of the 20% VS was measured as 5 nm using AFM (Fig. 1) and CMP was not used to smooth the cross-hatching. SiGe alloy compositions on fully processed devices were confirmed by SIMS and electron dispersive spectroscopy. Dual channel architectures, comprising a compressively strained Si0.7 Ge0.3 layer grown between the strained Si surface channel and a Si0.85Ge0.15VS were also grown. Strained Si/SiGe device fabrication followed a conventional 0.25 μm CMOS process. A gate oxide was thermally grown at 800 °C, resulting in a 6 nm gate oxide. Polysilicon was deposited and devices down to 150 nm gate length were patterned using electron-beam lithography. As and P were implanted into the source, drain and gate and annealed at 1050 °C for 20 sec. Back-end processing comprised deposited silox and BPSG with Al metalisation. Control Si devices had a B retrograde well implanted while strained Si/SiGe devices had in-situ doped B ~7x10 cm. 3. Electrical Characteristics Transconductance (gm) curves as a function of VS alloy composition are shown in Fig. 2a for 0.3 μm MOSFETs. The peak enhancement in maximum gm (g m ) over Si control devices is 240% for a Si0.7Ge0.3VS at a drain voltage (Vd) = 0.1 V. At Vd = 1.2 V the maximum enhancement in gm max compared with Si devices is 65% (Fig. 2b). For 10 μm gate length devices the maximum enhancement in gm max over the Si controls is 120%. The smaller enhancements in gm max in shorter channel length devices is due to SiGe self-heating. This is illustrated in Fig. 3 by the decrease in drain current (Id) at higher Vd for the strained Si0.75Ge0.25 device, which is not observed for the Si control device. Id is significantly increased for the strained Si/SiGe device compared with the Si control. At Vg-Vt = 2 V and Vd = 1 V, Id is 0.65 mA/μm for the Si0.75Ge0.25 device and 0.4 mA/μm for the Si control, an enhancement exceeding 60%. The higher channel mobility also causes the lower knee voltage on the I-V curves on Fig. 3. The field-effect mobility (μe) characteristics are shown in Fig. 4. The peak mobility for the strained Si0.75Ge0.25 device is enhanced by 115% compared with the peak mobility of the Si control device. These are the first results demonstrating that strained Si MOSFET mobility degrades at higher VS Ge compositions. The strained Si/SiGe devices exhibited lower threshold voltages than unstrained control devices (Fig. 5). The channel doping in all the devices was designed to be the same and CV measurements (Fig. 6) confirmed that there were no appreciable differences in the electrical oxide thickness (~ 6.5 nm) between the devices shown. The physical oxide thickness is measured as approximately 6 nm by TEM for the Si0.85Ge0.15VS MOSFET, in good agreement with the CV data. Therefore the differences in Vt observed are primarily due to the differing electron affinities of the materials, and Vg-Vt was used in comparisons of electrical data. Fig. 7 shows log Id vs. Vg–Vt characteristics. The on-state performance is not degraded until the VS Ge composition reaches 30% (Fig. 2) but the off-state performance deteriorates at 20%. Since the sub-threshold characteristic is highly sensitive to the gate oxide interface trap density, the results indicate the effect of Ge diffusion to the surface of the strained Si channel is a negligible until a Si0.7Ge0.3 VS is used. The μfe Eeff relation for single and dual channel Extended Abstracts of the 2003 International Conference on Solid State Devices and Materials, Tokyo, 2003, 722 A-9-4 pp. 722-723