A. Gehring

Method for predicting f/sub T/ for carbon nanotube FETs

A method based on a generic small-signal equivalent circuit for field-effect transistors is proposed for predicting the unity-current-gain frequency f/sub T/ for carbon-nanotube devices. The key to the useful implementation of the method is the rigorous estimation of the values for the components of the equivalent circuit. This is achieved by numerical differentiation of the charges and currents resulting from self-consistent solutions to the equations of Schrodinger and Poisson. Sample results are presented, which show that f/sub T/ can have a very unusual dependence on the gate-source bias voltage. This behavior is due mainly to the voltage dependence of the transconductance and capacitance in the presence of quasi-bound states in the nanotube.

Modeling of tunneling current and gate dielectric reliability for nonvolatile memory devices

We present a hierarchy of tunneling models suitable for the two- and three-dimensional simulation of logic and nonvolatile semiconductor memory devices. The crucial modeling topics are comprehensively discussed, namely, the modeling of the energy distribution function in the channel to account for hot-carrier tunneling, the calculation of the transmission coefficient of single and layered dielectrics, the influence of quasi-bound states in the inversion layer, the modeling of static and transient defect-assisted tunneling, and the modeling of dielectric degradation and breakdown. We propose a set of models to link the gate leakage to the creation of traps in the dielectric layer, the threshold voltage shift, and eventual dielectric breakdown. The simulation results are compared to commonly used compact models and measurements of logic and nonvolatile memory devices.

Simulation of hot-electron oxide tunneling current based on a non-Maxwellian electron energy distribution function

For the simulation of gate oxide tunneling currents in sub-quarter-micron devices, the correct modeling of the electron energy distribution function is crucial. Our approach is based on a recently presented transport model which accounts for six moments of the Boltzmann transport equation. A corresponding analytical model for the electron energy distribution function shows good agreement with Monte Carlo data. Using this model, we show that the gate current behavior of short-channel devices can be reproduced correctly. This is not the case for the heated Maxwellian approximation which leads to a massive overestimation of gate currents especially for devices with small gate lengths. We develop a formalism to distinguish between cases where the heated Maxwellian distribution delivers correct results and cases where it overestimates the tunneling current at low drain bias and find that for oxide thicknesses around 2 nm, the heated Maxwellian approximation is only valid for electron temperatures below about 1...

Separated carrier injection control in carbon nanotube field-effect transistors

The ambipolar behavior limits the performance of carbon nanotube field-effect transistors. A double-gate device is proposed to suppress this behavior. In this device, the first gate controls carrier injection at the source contact and the second one controls carrier injection at the drain contact, which can be used to suppress parasitic carrier injection. The effect of the second gate voltage on the performance of the device has been investigated. Our results indicate that by applying a proper voltage range to the second gate, improved device characteristics can be achieved.

Improving the ambipolar behavior of Schottky barrier carbon nanotube field effect transistors

Due to the capability of ballistic transport, carbon nanotube field-effect transistors (CNTFETs) have been studied in recent years as a potential alternative to CMOS devices. CNTFETs can be fabricated with ohmic or Schottky type contacts. We focus here on Schottky barrier CNTFETs which operate by modulating the transmission coefficient of Schottky barriers at the contact between the metal and the carbon nanotube (CNT). The ambipolar behavior of Schottky barrier CNTFETs limits the performance of these devices. We show that a double gate design can suppress the ambipolar behavior considerably. In this structure, for an n-type device, the first gate which is near the source controls electron injection and the second gate which is near the drain suppresses hole injection. The voltage of the second gate can be set to a constant voltage or to the drain voltage. We investigated the effect of the second gate voltage on the performance of the device and finally discuss the advantages and disadvantages of these designs.

Optimization of single-gate carbon-nanotube field-effect transistors

The performance of Schottky-barrier carbon-nanotube field-effect transistors (CNTFETs) critically depends on the device geometry. Asymmetric gate contacts, the drain and source contact thickness, and inhomogenous dielectrics above and below the nanotube influence the device operation. An optimizer has been used to extract geometries with steep subthreshold slope and high I/sub on//I/sub off/ ratio. It is found that the best performance improvements can be achieved using asymmetric gates centered above the source contact, where the optimum position and length of the gate contact varies with the oxide thickness. The main advantages of geometries with asymmetric gate contacts are the increased I/sub on//I/sub off/ ratio and the fact that the gate voltage required to attain minimum drain current is shifted toward zero, whereas symmetric geometries require V/sub g/=V/sub d//2. Our results suggest that the subthreshold slope of single-gate CNTFETs scales linearly with the gate-oxide thickness and can be reduced by a factor of two reaching a value below 100 mV/dec for devices with oxide thicknesses smaller than 5 nm by geometry optimization.

Simulation of carrier transport in carbon nanotube field effect transistors

We discuss models to describe carrier transport in axial and lateral type carbon nanotube field-effect transistors (CNT-FET). Operation is controlled by the electric field from the gate contact which can lead to strong band bending, allowing carriers to tunnel through the interface barrier. We find that the difference between lateral and axial CNT-FETs is that in devices with axially aligned carbon nanotubes tunneling becomes negligible and transport can be modeled by means of thermionic emission. In lateral CNT-FETs tunneling dominates, for which we present a model for the transmission coefficient using the WKB method and a non-parabolic dispersion relation. The simulated output and transfer characteristics show reasonable agreement with experimental data for both lateral and axial CNT-FET devices.

Impact of NBTI-driven parameter degradation on lifetime of a 90nm p-MOSFET

NBTI has emerged as a major reliability concern for the electrical stability of advanced CMOS technology. We report an experimental and simulation study for the NBTI mechanism in a high-performance p-MOSFET. Various stress experiments were performed in order to analyze the degradation of the key device parameters, V/sub T/ and I/sub Dsat/. The presently leading reaction-diffusion (R-D) model is used to study the interface trap generation based on the diffusion and accumulation of released hydrogen in the gate oxide. The long-time degradation was simulated in order to estimate the NBTI lifetime which depends on the applied gate voltages and frequencies. The lifetime extension under higher frequency operation was analyzed at a typical supply voltage of 1.45V with a tolerance of /spl plusmn/50mV. An unexpected long lifetime extension between six times and twenty times of the DC lifetime was found for an operation with a 10MHz gate signal.

Modeling of Tunneling Currents for Highly Degraded CMOS Devices

We present a model for tunneling currents in highly degraded CMOS devices. In this field not only well established tunneling mechanisms like Fowler-Nordheim and direct tunneling are important to consider, but also defect-assisted tunneling mechanisms such as elastic and inelastic trap-assisted tunneling and hopping processes between defects. In our work the interaction of several defects in the tunneling process is taken into account. The multi-trap assisted tunneling current is dominant for heavily degraded devices with dielectric thicknesses above approximately 3-4 nm. The filling of traps with carriers leads to space charge and is thus changing device parameters such as threshold-voltage or saturation currents.

Silicon carbide accumulation-mode laterally diffused MOSFET

We present a new accumulation-mode structure for silicon carbide laterally diffused MOSFETs. Key parameters that alter the device performance have been optimized using the device simulator MINIMOS-NT. The relationship between blocking and driving capability of the structure has been analyzed. Excellent I-V characteristics with significant improvement in the reduction of the gate bias voltage has been achieved. A blocking voltage of 1460 V with a small leakage current, a considerably lower specific on resistance of 93 m/spl Omega//spl middot/cm/sup 2/ and a fairly large advantage in electrical performance and device reliability were achieved.