H. Ceric
Vienna University of Technology
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Publication
Featured researches published by H. Ceric.
Microelectronics Reliability | 2010
R. L. de Orio; H. Ceric; Siegfried Selberherr
Electromigration failure is a major reliability concern for integrated circuits. The continuous shrinking of metal line dimensions together with the interconnect structure arranged in many levels of wiring with thousands of interlevel connections, such as vias, make the metallization structure more susceptible to failure. Mathematical modeling of electromigration has become an important tool for understanding the electromigration failure mechanisms. Therefore, in this work we review several electromigration models which have been proposed over the years. Starting from the early derivation of Blacks equation, we present the development of the models in a somewhat chronological order, until the recent develop- ments for fully three-dimensional simulation models. We focus on the most well known, continuum physically based models which have been suitable for comprehensive TCAD analysis.
Microelectronics Reliability | 2010
Stanislav Tyaginov; Ivan Starkov; Oliver Triebl; Johann Cervenka; Christoph Jungemann; Sara Carniello; Jong Mun Park; Hubert Enichlmair; M. Karner; Ch. Kernstock; Ehrenfried Seebacher; Rainer Minixhofer; H. Ceric; Tibor Grasser
We refine our approach for hot-carrier degradation modeling based on a thorough evaluation of the carrier energy distribution by means of a full-band Monte–Carlo simulator. The model is extended to describe the linear current degradation over a wide range of operation conditions. For this purpose we employ two types of interface states, either created by single- or by multiple-electron processes. These traps apparently have different densities of states which is important to consider when calculating the charges stored in these traps. By calibrating the model to represent the degradation of the transfer characteristics, we extract the number of particles trapped by both types of interface traps. We find that traps created by the single- and multiple-electron mechanisms are differently distributed over energy with the latter shifted toward higher energies. This concept allows for an accurate representation of the degradation of the transistor transfer characteristics.
IEEE Transactions on Device and Materials Reliability | 2009
H. Ceric; R. L. de Orio; Johann Cervenka; Siegfried Selberherr
The demanding task of assessing long-time interconnect reliability can only be achieved by combination of experimental and technology computer-aided design (TCAD) methods. The basis for a TCAD tool is a sophisticated physical model which takes into account the microstructural characteristics of copper. In this paper, a general electromigration model is presented with special focus on the influence of grain boundaries and mechanical stress. The possible calibration and usage scenarios of electromigration tools are discussed. The physical soundness of the model is proved by 3-D simulations of typical dual-damascene structures used in accelerated electromigration testing.
IEEE Transactions on Device and Materials Reliability | 2010
Rui Huang; Werner Robl; H. Ceric; Thomas Detzel; Gerhard Dehm
Electroplated copper films are known to change their microstructure due to the self-annealing effect. The self-annealing effect of electroplated copper films was investigated by measuring the time dependence of the film stress and sheet resistance for different layer thicknesses between 1.5 and 20 ¿m. While the sheet resistance was found to decrease as time elapsed, a size-dependent change in film stress was observed. Films with the thickness of 5 ¿m and below decrease in stress, while thicker films initially reveal an increase in film stress followed by a stress relaxation at a later stage. This behavior is explained by the superposition of grain growth and grain-size-dependent yielding.
international conference on simulation of semiconductor processes and devices | 2011
Stanislav Tyaginov; Ivan Starkov; Oliver Triebl; H. Ceric; Tibor Grasser; Hubert Enichlmair; Jong-Mun Park; Christoph Jungemann
We propose a physics-based model for hot-carrier degradation (HCD), which is able to represent HCD observed in n-channel high-voltage MOSFETs with different channel length with a single set of physical parameters. Our approach considers not only damage produced by channel electrons but also by secondary generated channel holes. Although the contribution of the holes to the total defect creation is smaller compared to that of electrons, their impact on the linear drain current is comparable with the electronic one. The reason behind this trend is that hole-induced traps are shifted towards the source, thereby more severely affecting the device behavior.
international symposium on the physical and failure analysis of integrated circuits | 2010
Stanislav Tyaginov; Ivan Starkov; Oliver Triebl; Johann Cervenka; Christoph Jungemann; Sara Carniello; Jong-Mun Park; Hubert Enichlmair; M. Karner; Ch. Kernstock; Ehrenfried Seebacher; Rainer Minixhofer; H. Ceric; Tibor Grasser
We propose and verify a model for hot carrier degradation based on the exhaustive evaluation of the energy distribution function for charge carriers in the channel by means of a full-band Monte-Carlo device simulator. This approach allows us to capture the interplay between “hot” and “colder” electrons and their contribution to the damage build-up. In fact, particles characterized by higher energy are able to produce interface traps by a single-carrier process while colder ones trigger multivibrational mode excitation of a Si-H bond. For the model validation we use long-channel MOSFETs and represent the degradation of the linear drain current. The single-carrier component dominates degradation (this is the usual tendency for long devices), however, the multiple-carrier process is still considerable being less and less pronounced as the source-drain stress voltage increases
STRESS-INDUCED PHENOMENA IN METALLIZATION: Eighth International Workshop on#N#Stress-Induced Phenomena in Metallization | 2006
H. Ceric; René Heinzl; Ch. Hollauer; Tibor Grasser; Siegfried Selberherr
The modifications and extensions of standard continuum models used for a description of material transport due to electromigration with models for the copper microstucture are studied. Copper grain boundaries and interfaces are modeled as a network of high diffusivity paths. Additionally, grain boundaries act as sites of vacancy recombination. The connection between mechanical stress and material transport is established for the case of strain build up induced by local vacancy dynamics and the anisotropy of the diffusivity tensor caused by these strains. High diffusivity paths are set on the surfaces of polyhedral domains representing distintcive grains. These polyhedral domains are connected by diffusive, electrical, and mechanical interface models. For a numerical solution a three‐dimensional finite element method is used.
Microelectronics Reliability | 2011
R. L. de Orio; H. Ceric; Siegfried Selberherr
A compact model for early electromigration failures in copper dual-damascene interconnects is proposed. The model is based on the combination of a complete void nucleation model together with a simple mechanism of slit void growth under the via. It is demonstrated that the early electromigration lifetime is well described by a simple analytical expression, from where a statistical distribution can be conveniently obtained. Furthermore, it is shown that the simulation results provide a reasonable estimation for the lifetimes.
IEEE Microwave and Wireless Components Letters | 2007
Masoud Movahhedi; Abdolali Abdipour; H. Ceric; Alireza Sheikholeslami; Siegfried Selberherr
We present a new formulation to implement the complex frequency shifted-perfectly matched layer (CFS-PML) for boundary truncation in 2-D vector finite-element time-domain method directly applied to Maxwells equations. It is shown that the proposed method is highly absorptive to evanescent modes when computing the wave interaction of elongated structures or sharp corners. The impact of the CFS-PML parameters on the reflection error is investigated and optimal choices of these parameters are derived
Microelectronics Reliability | 2012
R. L. de Orio; H. Ceric; Siegfried Selberherr
Electromigration induced failure development in a copper dual-damascene structure with a through silicon via (TSV) located at the cathode end of the line is studied. The resistance change caused by void growth under the TSV and the interconnect lifetime estimation are modeled based on analytical expressions and also investigated with the help of numerical simulations of fully three-dimensional structures. It is shown that, in addition to the high resistance increase caused by a large void, a small void under the TSV can also lead to a significant resistance increase, particularly in the presence of imperfections at the TSV bottom introduced during the fabrication process. As a consequence, electromigration failure in such structures is likely to have bimodal characteristics. The simulation results have indicated that both modes are important to be considered in order to obtain a more precise description of the interconnect lifetime distribution.