A. Gothenberg

Nonlinear Quantization in Low Oversampling Ratio Sigma-Delta Noise Shapers for RF Applications

Baseband signal processing for current base stations or 3rd generation mobile systems will impose high bandwidth and high VLSI integration demand. Many of the desired integration aspects can be satisfied with sigma-delta converter front-ends. However, under the technology constraints there are simultaneous requirements for high sample rate and low oversampling ratio in order to achieve the desired baseband width. In this paper, we present system architecture results for the 4th-order cascaded noise shaper architectures to be used in baseband front-ends. We show that the cascaded structures with proper scaling will satisfy simultaneous demand on linearity (spurious free dynamic range) and high SQNR with low oversampling ratio based on usage of multibit quantizers outside the actual signal noise shaping path. We also present results for nonlinear quantization effects in low oversampling ratio cascaded noise shaper architectures. We analyse the effect of the non-linearity in both the A/D and D/A-block in quantization error quantizer path for the 4th-order cascaded topology and the design constraints associated to the performance of the used A/D and D/A structures. The performance requirement for the multi-bit quantizer for high SQNR is shown for the case of low oversampling ratios. The results show that non-uniform quantization around zero input are far more crucial to the SQNR than nonlinear quantization deviating from the ideal transfer function. As the key difference to standard multibit quantizers, no special error correction or error distribution schemes are required; the linearity requirements are satisfied with 0.2 LSB accuracy of the few bit quantizer. Finally, the performance of non-linear quantization using multitone test signals are also shown.

Performance analysis of low oversampling ratio sigma-delta noise shapers for RF applications

Baseband signal processing for current base stations or 3rd generation mobile systems will impose high bandwidth and high VLSI integration demand. Many of the desired integration aspects can be satisfied with sigma-delta converter front-ends. However, under the technology constraints there are simultaneous requirements for high sample rate and low oversampling ratio in order to achieve the desired baseband width. In this paper, we present system architecture results for 4th-order cascaded noise shaper architectures for baseband front-ends and show that the cascaded structures with proper scaling will satisfy simultaneous demand on linearity (spurious free dynamic range) and high SQNR with low oversampling ratio based on usage of multibit quantizers outside the actual signal noise shaping path.

Analysis of clock jitter effects in wideband sigma-delta modulators for rf-applications

This paper presents a theoretical overview and analysis of the main types of clock jitter in a switched capacitor (SC) Sigma-Delta (/spl Sigma//spl Delta/) Analog-to-Digital-Converter (ADC). We start by defining the different types of jitter and proceed to analyze their impact both theoretically and by simulations. The main jitter assumption throughout this paper is that it is stochastic in nature. Using this assumption each jitter types effect on the /spl Sigma//spl Delta/ output is calculated and simulated. One type of jitter is often neglected in textbooks and other papers due to assumptions which need to be clarified. We conclude that it is important to consider this type of jitter because it has a strong impact. Furthermore, it is important to characterize each jitter type not only with severity but also how difficult it is to suppress or the likelihood of jitter presence which, of course, is dependent on architecture and application.

Modeling and analysis of substrate coupled noise in pipelined data converters

This paper presents methods to model and analyze substrate coupled noise in pipelined data converters. The substrate noise models covers substrate types, such as lightly and highly doped substrates, and the analyzes includes the effects on the pipelined data converter performance from a variety of noise shielding techniques, such as guarding and wells. Classical approaches to prevent noise are investigated. It is found that in some cases these traditional design rules are no longer suitable and have to be redefined.

Power-Supply and Substrate-Noise-Induced Timing Jitter in Nonoverlapping Clock Generation Circuits

This paper describes a study of power-supply noise and substrate noise impact on the timing properties of two nonoverlapping clock generation circuits that are typically used in sigma-delta modulators. The constituent logic blocks of the clock generation circuits are also individually characterized where special attention has been put on the inverter whose behavior is fully described in mathematical terms. The analytical model is verified with SPICE using 0.35-mum CMOS process parameters, and a reference simulation in 0.18 mum is also presented showing the trend of technology downscaling. Furthermore, the nonoverlapping clock generation circuits are characterized in the 0.18-mum process and the phenomenon of jitter peaking is described. Finally, all variations of connection configurations in the clock generation circuits are explored to reveal possible optimal configurations.

A study of nonlinearities for a frequency-locked loop principle [frequency synthesizer application]

This paper presents the effect of nonlinearities on data converter resolution. Two models, an exponential and a sinusoidal approach, are proposed to estimate the drop in signal to noise (+distortion) ratio (SNDR). Matlab simulation results predict a loss between 1 dB and 10 dB when introducing a nonlinearity error of up to 2 LSB. These models were used to study the performance loss of a multi-bit converter when used in a frequency synthesizer architecture.

Performance analysis of sampling switch structures for wideband sigma-delta noise shapers for RF applications

The sampling switch of a wideband sigma-delta noise shaper for RF applications is a very critical component as any nonlinearities within reduces the spurious free dynamic range, SFDR, of the whole modulator. Errors due to nonlinearities are carried on to all other processing stages. The analysis investigates a variety of sampling switches. It is found that apart from insignificant dependence of input voltage level the bootstrap sampling switch also has a significant higher SFDR over the entire bandwidth.

A method for stability and performance analysis of low oversampling ratio higher order sigma delta noise shaper architectures

This paper demonstrates a method for determining the stability and sensitivity of feedback coefficient variations of sigma delta noise shapers using a model based on parameterized quantization gain which varies from sample to sample. The method is demonstrated for two types of sigma delta converter structures, the 4th order multibit cascaded structure and the 5th order single stage 1-bit structure.