Bingxin Li

Efficient and accurate modeling of power supply noise on distributed on-chip power networks

In this paper, we propose an efficient and accurate modeling technique for power supply noise estimation over on-chip power lines which are modeled as distributed RCL networks. With this model, peak noise on the power lines that includes on-chip resistive and inductive voltage drops, switching noise on packages, and on-chip decoupling effects, can be computed very efficiently and accurately. The model is verified by SPICE simulations.

Implementation of a low power 128-point FFT

In this paper a low power 128 point fast Fourier transform (FFT) processor is implemented based on our new VLSI-oriented FFT algorithm-radix-2/4/8, which can effectively minimize the number of complex multiplications. A new management of the on-chip memory further reduce its power consumption. This FFT processor has been designed in 0.6 /spl mu/m 3.3 V triple-metal CMOS process with an area of 10 mm/sup 2/. The chip is capable of computing a 128 point FFT every 3 /spl mu/s and the power dissipation is 400 mW at 50 MHz input frequency.

Global interconnect design for high speed ULSI and system-on-package

In this paper, interconnects are treated as important design objects for high performance ASICs in deep submicron technology. Their electrical performance and optimal layout schemes are studied with regards to the interconnect delay and signal integrity issues. The maximum usable interconnect length for signal integrity is defined and referred to as the design guidelines. The study emphasizes high speed ULSI on-chip global bus and off-chip interconnects for system-on-package-an attractive system integration route before system-on-chip. The models and design guidelines developed from this paper is useful for a rule-based interconnect model as well as for building a parameterized dynamic interconnect library in advanced ASIC designs.

Hierarchical modeling of sigma delta modulators for noise coupling analysis

In this paper a hierarchical modeling strategy of a sigma delta modulator for mixed signal coupling analysis is presented. In this hierarchical model only the key components which are important to noise or disturbance analysis are implemented on the transistor level, the other parts are realized in a behavioral model which is written in Analog HDL. The simulation speed can be improved by an order of magnitude. With this method, fast and reasonably accurate estimation for coupled noise in mixed-signal IC design can be achieved. A 5th order sigma delta modulator is used as a demonstration to show the intrinsic noise analysis and the substrate coupling noise analysis.

A structure of cascading multi-bit modulators without dynamic element matching or digital correction

A new structure of cascading multi-bit Sigma Delta modulators is proposed in this paper. Using a multi-bit quantizer in each stage, the modulators performance is largely improved. Furthermore this structure does not require any dynamic element matching or digital correction circuit to attenuate the non-linearity error. This is because the modulators first stage uses a multi-bit quantizer, but only the most significant bit is used to generate the feedback. By this way the non-linearity error is eliminated. Simulation results are demonstrated with circuit non-idealities considered.

Optimization of analog modeling and simulation

In this paper a comprehensive method of analog modeling and simulation is given, in which models at different hierarchy levels are used in an optimized combination. To meet the conflicting requirements of simulation efficiency and accuracy, analog HDL is used as the bridge between high level behavioral models and low level transistor models. In this way both requirements are satisfied. A 5th order oversampling sigma-delta modulator is employed to demonstrate the design and modeling practice.

A Second Order Multi-Bit Sigma Delta Modulator with Single-Bit Feedback

Multi-bit Sigma Delta modulators suffer from the DAC non-linearity problem and often need complicated Dynamic Element Matching (DEM) circuits. Combining a multi-bit quantizer and a single-bit DAC eliminates the need of DEM circuits, simplifies the design, and reduces the power consumption. Using a digital circuit to compensate the truncation error caused by cutting the multi-bit feedback to single-bit, the structure can achieve the same noise transfer function as a conventional multi-bit modulator. One drawback is that the signal scaling in such a structure lowers the overall resolution. In this paper the influence of signal scaling is analyzed and a design example given. A second order 3-bit modulator is fabricated in 0.35 μm CMOS process, achieving 82 dB dynamic range at OSR = 128 and a peak SNDR of 73.1 dB.

A method for stability and performance analysis of low oversampling ratio higher order sigma delta noise shaper architectures

This paper demonstrates a method for determining the stability and sensitivity of feedback coefficient variations of sigma delta noise shapers using a model based on parameterized quantization gain which varies from sample to sample. The method is demonstrated for two types of sigma delta converter structures, the 4th order multibit cascaded structure and the 5th order single stage 1-bit structure.

A Design of Operational Amplifier for Sigma Delta Modulators Using 0.35um CMOS Process

An operational amplifier designed with 0.35um CMOS technology is presented. All the transistors are realized with minimum or near-minimum channel length. As the short channel length causes performance degradation, a proper operational amplifier structure is selected to compensate the performance degradation. The op amp is designed to meet the requirement of high-speed high-resolution sigma delta modulators. It has a folded-cascode first stage and a class-A output stage. It features a DC gain of 78dB, an open-loop unity-gain frequency of 266MHZ, a slew rate of 650V/us, and consumes 10.2mW from a +/−1.5V power supply. High level simulation is used to evaluate the OTA performance in sigma delta modulators.

A new cascaded sigma delta modulator structure using multi-bit quantizers combined with single-bit feedback

A new cascaded structure is presented using two multi-bit quantizers in its two stages. In the first stage only the most-significant-bit of the quantizer output is used in the feedback loop, so high linearity can be achieved just as using a single-bit quantizer. Furthermore, as the first stage uses a multi-bit quantizer, the quantization error is very small. Thus this quantization error could be amplified by a gain A before it is sent to the second stage. Using a digital error cancelling network, the quantization error of the second stage can be reduced by a factor of 1/A.