A. Junique

The ALICE TPC, a large 3-dimensional tracking device with fast readout for ultra-high multiplicity events

The design, construction, and commissioning of the ALICE Time-Projection Chamber (TPC) is described. It is the main device for pattern recognition, tracking, and identification of charged particles in the ALICE experiment at the CERN LHC. The TPC is cylindrical in shape with a volume close to 90 m(3) and is operated in a 0.5T solenoidal magnetic field parallel to its axis. In this paper we describe in detail the design considerations for this detector for operation in the extreme multiplicity environment of central Pb-Pb collisions at LHC energy. The implementation of the resulting requirements into hardware (field cage, read-out chambers, electronics), infrastructure (gas and cooling system, laser-calibration system), and software led to many technical innovations which are described along with a presentation of all the major components of the detector, as currently realized. We also report on the performance achieved after completion of the first round of stand-alone calibration runs and demonstrate results close to those specified in the TPC Technical Design Report

The ALICE TPC front end electronics

In this paper we present the front end electronics for the time projection chamber (TPC) of the ALICE experiment. The system, which consists of about 570000 channels, is based on two basic units: (a) an analogue ASIC (PASA) that incorporates the shaping-amplifier circuits for 16 channels; (b) a mixed-signal ASIC (ALTRO) that integrates 16 channels, each consisting of a 10-bit 25-MSPS ADC, the baseline subtraction, tail cancellation filter, zero suppression and multi-event buffer. The complete readout chain is contained in front end cards (FEC), with 128 channels each, connected to the detector by means of capton cables. A number of FECs (up to 25) are controlled by a readout control unit (RCU), which interfaces the FECs to the data acquisition (DAQ), the trigger, and the detector control system (DCS). A function of the final electronics (1024 channels) has been characterized in a test that incorporates a prototype of the ALICE TPC as well as many other components of the final set-up. The tests show that the system meets all design requirements. Originally conceived and optimized for the time projection chamber (TPC) of the ALICE experiment, its architecture and programmability make this system suitable for the readout of a wider class of detectors.

The ALICE TPC readout control unit

The front end electronics for the ALICE time projection chamber (TPC) consists of about 560000 channels packed in 128-channel units (front end card). Every front end card (FEC) incorporates the circuits to amplify, shape, digitize, process and buffer the TPC pad signals. From the control and readout point of view the FECs are organized in 216 partitions, each being an independent system steered by one readout control unit (RCU). The RCU, which is physically part of the on-detector electronics, implements the interface to the data acquisition (DAQ), the trigger and timing circuit (TTC) and the detector control system (DCS). It broadcasts the trigger and clock information to the FECs, performs the initialization and readout via a high bandwidth bus, and implements monitoring and safety control functions via a dedicated I2C-like link. This paper addresses the architecture and the system performance of the RCU

Monolithic active pixel sensor development for the upgrade of the ALICE inner tracking system

ALICE plans an upgrade of its Inner Tracking System for 2018. The development of a monolithic active pixel sensor for this upgrade is described. The TowerJazz 180 nm CMOS imaging sensor process has been chosen as it is possible to use full CMOS in the pixel due to the offering of a deep pwell and also to use different starting materials. The ALPIDE development is an alternative to approaches based on a rolling shutter architecture, and aims to reduce power consumption and integration time by an order of magnitude below the ALICE specifications, which would be quite beneficial in terms of material budget and background. The approach is based on an in-pixel binary front-end combined with a hit-driven architecture. Several prototypes have already been designed, submitted for fabrication and some of them tested with X-ray sources and particles in a beam. Analog power consumption has been limited by optimizing the Q/C of the sensor using Explorer chips. Promising but preliminary first results have also been obtained with a prototype ALPIDE. Radiation tolerance up to the ALICE requirements has also been verified.

Radiation hardness and detector performance of new 180nm CMOS MAPS prototype test structures developed for the upgrade of the ALICE Inner Tracking System

The features of the 180nm TowerJazz1 CMOS technology allow for the first time the use of CMOS Monolithic Active Pixel Sensors (MAPS) under the harsh operational conditions of the LHC experiments. The stringent requirements of the ALICE Inner Tracking System (ITS) in terms of material budget, radiation hardness, readout speed and a low power consumption have thus lead to the choice of MAPS as baseline technology option for the recently approved upgrade of the ITS and are the key drivers for R&D efforts on basic transistor and Explorer and MIMOSA pixel sensor prototypes produced in TowerJazz technology. Though the radiation loads expected for the ITS are below those of ATLAS and CMS, it is however necessary to assess the radiation hardness for ITS MAPS prototypes. Total Ionizing Dose (TID) radiation hardness has been established for basic transistor structures using a 60keV X-ray machine. The main operational characteristics and detection properties such as noise, charge collection efficiency and signal over noise ratio of Explorer-0 and MIMOSA32 and MIMOSA34 pixel sensor prototypes have been studied using X-rays (55Fe) and test beams at CERN and DESY before and after Non Ionizing Energy Loss (NIEL) and TID irradiation. In this paper the results of these R&D activities will be presented and discussed.

MAPS development for the ALICE ITS upgrade

Monolithic Active Pixel Sensors (MAPS) offer the possibility to build pixel detectors and tracking layers with high spatial resolution and low material budget in commercial CMOS processes. Significant progress has been made in the field of MAPS in recent years, and they are now considered for the upgrades of the LHC experiments. This contribution will focus on MAPS detectors developed for the ALICE Inner Tracking System (ITS) upgrade and manufactured in the TowerJazz 180 nm CMOS imaging sensor process on wafers with a high resistivity epitaxial layer. Several sensor chip prototypes have been developed and produced to optimise both charge collection and readout circuitry. The chips have been characterised using electrical measurements, radioactive sources and particle beams. The tests indicate that the sensors satisfy the ALICE requirements and first prototypes with the final size of 1.5 × 3 cm2 have been produced in the first half of 2014. This contribution summarises the characterisation measurements and presents first results from the full-scale chips.

Front end optimization for the monolithic active pixel sensor of the ALICE Inner Tracking System upgrade

ALICE plans to replace its Inner Tracking System during the second long shut down of the LHC in 2019 with a new 10 m2 tracker constructed entirely with monolithic active pixel sensors. The TowerJazz 180 nm CMOS imaging Sensor process has been selected to produce the sensor as it offers a deep pwell allowing full CMOS in-pixel circuitry and different starting materials. First full-scale prototypes have been fabricated and tested. Radiation tolerance has also been verified. In this paper the development of the charge sensitive front end and in particular its optimization for uniformity of charge threshold and time response will be presented.

Upgrade of the ALICE-TPC read-out electronics

The ALICE experiment at CERN LHC employs a large volume time projection chamber (TPC) as its main tracking device. Instigated by analyses indicating that the high level trigger is capable of sifting events with rare physics probes, it is endeavoured to read out the TPC an order of magnitude faster then was reckoned during the design of its read-out electronics. Based on an analysis of the read-out performance of the current system, an upgrade of the front-end read-out network is proposed. The performance of the foreseen architecture is simulated with raw data from real 7 TeV pp collisions. Events are superimposed in order to emulate the future ALICE running conditions: high multiplicity events generated either by PbPb collisions or by the superposition (pile-up) of a large number of pp collisions. The first prototype of the main building block has been produced and characterised, demonstrating the feasibility of the approach.

A distributed, heterogeneous control system for the ALICE TPC electronics

The ALICE detector is a dedicated heavy-ion detector currently built at the large hadron collider (LHC) at CERN. The detector consists of several sub-detectors each of them forming a highly complex device. The detector control system (DCS) covers the task of controlling, configuring and monitoring of the detector system. Since the experiment was running in a radiation environment, fault tolerance, error correction and system stability in general are major concerns. A system consisting of independently running layers has been designed, the functionality layers are running on a large number of nodes and sub-nodes. An autonomous single-board computer, the DCS board, has been developed which allows one to run the operating system Linux in an embedded environment and to perform tasks related to the hardware devices. Further custom hardware devices have been developed covering specific tasks and serving as sub-nodes. These devices together with standard computers in higher control layers form a distributed control system. This article focused on the concept and architecture of the DCS for the front-end electronics of the time-projection chamber (TPC) and present results and experiences from system integration tests.

A CMOS 0.18 μm 600 MHz clock multiplier PLL and a pseudo-LVDS driver for the high speed data transmission for the ALICE Inner Tracking System front-end chip

This work presents the 600 MHz clock multiplier PLL and the pseudo-LVDS driver which are two essential components of the Data Transmission Unit (DTU), a fast serial link for the 1.2 Gb/s data transmission of the ALICE inner detector front-end chip (ALPIDE). The PLL multiplies the 40 MHz input clock in order to obtain the 600 MHz and the 200 MHz clock for a fast serializer which works in Double Data Rate mode. The outputs of the serializer feed the pseudo-LVDS driver inputs which transmits the data from the pixel chip to the patch panel with a limited number of signal lines. The driver drives a 5.3 m-6.5 m long differential transmission line by steering a maximum of 5 mA of current at the target speed. To overcome bandwidth limitations coming from the long cables the pre-emphasis can be applied to the output. Currents for the main and pre-emphasis driver can individually be adjusted using on-chip digital-to-analog converters. The circuits will be integrated in the pixel chip and are designed in the same 0.18 μm CMOS technology and will operate from the same 1.8 V supply. Design and test results of both circuits are presented.