A.K. Mal

An accurate slew metric for on-chip VLSI interconnect using Weibull distribution function

Slew rate determines the ability of a device to handle the varying signals. Determination of the slew rate to a good proximity is thus essential for efficient design of high speed CMOS integrated circuits. This in turn estimates the output switching surges in the device. Interconnect slew has become a crucial bottleneck for any high density and high speed VLSI circuits. In this paper we have proposed an accurate and efficient model to compute the slew metric of on-chip interconnect of high speed CMOS VLSI deigns. Our slew metric is based on the weibull distribution function. Comparison of simulation results with other established models justifies the accuracy of our slew approach.

An Explicit Approach for Delay Evaluation for On-Chip RC Interconnects Using Beta Distribution Function by Moment Matching Technique

As the technology scales down to nanometer regime, interconnect delay is more dominant than gate delay. Many approaches primarily concentrated to find the interconnect delay rather than gate delay so that one can increase the speed of the circuit by simply decreasing the interconnect delay. Several approaches have been proposed to find the interconnect delay accurately and efficiently. By considering the impulse responses of linear circuit as a Probability Distribution Function (PDF), Elmore first estimated the value of interconnect delay. Several approaches have been proposed after Elmore Delay metric like PRIMO, AWE, h-gamma, WED, D2M etc. and are proven to be more accurate than Elmore delay metric. But they suffer from computational complexity when using in total IC design processes. From then onwards many researchers are trying to get a simplified and accurate expressions for interconnect delay by using different techniques and by considering different Probability Distribution Functions (PDF) as their impulse responses. Our work presents a closed form formula for on-chip VLSI RC interconnects delay. Delay metric is obtained by matching circuit moments to the Beta distribution function. The delay metric can be easily implemented for both step and ramp inputs by using a single look-up table. By simply calculating first two circuit moments we can find the interconnect delay of the linear circuit and the computation is also less when compared to other approaches which involve greater computational complexity. As impulse response of the linear circuit matches, in most of the cases, with the Probability Distribution Function (PDF) of Beta Distribution, this method of finding interconnect delay can be used in many linear circuits. The accuracy of our model is justified with the results compared with that of SPICE simulations and the models that have already being proposed with other probability distribution function.

An explicit approach for bandwidth evaluation of on-chip VLSI RC interconnects with current mode signaling technique

Scarcity of bandwidth demands the efficient use of it for high speed and high data rate transmission systems in VLSI Design and hence an accurate estimation of bandwidth of on-chip VLSI interconnects has become a crucial and an important issue. Current-mode signaling significantly increases the bandwidth of on-chip interconnects compared to voltage mode signaling. A closed form formula for current mode is necessary for estimation of bandwidth for VLSI systems. In this paper, an explicit bandwidth expression is derived by calculating the node voltages of distributed RC line using modified nodal analysis (MNA). Our model is based on the second order transfer function approximation of distributed RC lines. Comparison of results with that of the SPICE models justifies the accuracy of our approach.

Delay Estimation for On-Chip VLSI Interconnect using Weibull Distribution Function

In deep sub-micrometer (DSM) regime the on-chip interconnect delay is significantly more dominating than the gate delay. Several approaches have been proposed to capture the interconnect delay accurately and efficiently. By interpreting the impulse response of a linear circuit as a probability distribution function (PDF), Elmore first estimated the interconnect delay. Several other approaches like PRIMO, AWE, h-Gamma, WED, D2M etc. have been reported so far, which are shown to be more accurate delay estimation compared to Elmore delay metric. But they suffer from computational complexity when using in the total IC design processes. Our work presents a closed form formula for interconnect delay. The delay metric is derived by matching circuit moments to the Weibull distribution. The delay metric can be easily implemented for both step and ramp inputs by using a single look-up table. Experiments validate the effectiveness of the delay metric for nets from a real industrial design.

A Novel Power Estimation Method for On-chip VLSI Distributed RLCG Global Interconnects Using Model Order Reduction Technique

Due to high packaging density of components, power is increasingly becoming the bottleneck for the design of high performance VLSI circuits. It is essential to analyze how the various components of power are likely to scale in the future, thereby identifying the key problematic areas. This is an important fact because the conventional design, analysis, and synthesis of VLSI circuits are based on the assumption that gates are the main sources of on-chip power consumption. While most analysis focus on the timing aspects of interconnects, power consumption is also important. In this paper, the power distribution estimation of interconnects is studied using a reduced-order model. The relation between power consumption and the poles and residues of a transfer function is derived, and an appropriate driver model is developed, allowing power consumption to be computed efficiently. At higher frequency of operations, of the order of few GHz, the interconnect is to be analyzed with a distributed RLCG model. Because at very high frequency, the dielectric material deviates from it’s ideal nature. This gives rise to the shunt conductance matrices. In this paper we have considered the high frequency effects and modeled the interconnect as distributed RLCG segments to compute the interconnect power dissipation. The results obtained from SPICE simulation justify the accuracy of our model.

Crosstalk aware bandwidth modeling for distributed on-chip RLCG interconnects using difference model approach

In case of very high frequency as in Giga-scale (GHz), no longer can interconnects be treated as mere delays or lumped RC networks. The most common simulation model for interconnects is the distributed RC and RLC model. The impact of interconnects on circuit performance in both the analog and digital domains is ever increasing. Unfortunately, this model has many limitations which can lead to inaccurate simulations if not modeled correctly. Crosstalk, ringing and reflection are just some of the issues that need to be addressed and then circumvented or utilized. The traditional analysis of crosstalk in a transmission line begins with a lossless LC representation, yielding a wave equation governing the system response. With the reduction of distances between wires in deep sub-micron technologies, coupling capacitances are becoming significant. This increase in capacitance gives rise to noise which is capable of propagating a logical fault. A bad evaluation of the crosstalk could be at the origin of a malfunction of the circuit. Cross talk can be analyzed by computing the signal linkage between aggressor or attacker nets and victim nets. The attacker net carries a signal that couples to the victim net through the parasitic capacitance. To determine the effects that this cross talk will have on circuit operation, the resulting delays and logic levels for the victim nets must be computed. This paper proposes a difference model approach to derive a crosstalk aware bandwidth estimation method in the transform domain. A closed form solution for bandwidth is obtained by incorporating initial conditions using difference model approach for distributed RLCG interconnects. The simulation results justify the accuracy of our approach.

Closed Form Bandwidth Expression for Distributed On-chip RLCG Interconnects

With the increasing levels of on-chip integration, more functional units are integrated onto a single die, the logic delays decrease due to faster transistors. At the same time, local interconnect delays similarly improve because the physical size of circuit blocks decrease, and the local interconnect spans shorter distances. During the interconnect design process, multiple design criteria are considered, such as delay, power, bandwidth, and noise. Performance of any high speed VLSI circuit depends on the bandwidth as it decreases with increase in the length of interconnects. The impact of interconnects on circuit performance in both the analog and digital domains is ever increasing. In case of very high frequency as in Gigascale (GHz), no longer can interconnects be treated as mere delays or lumped RC networks. The most common simulation model for interconnects is the distributed RLC model. Unfortunately, this model has many limitations which can lead to inaccurate simulations if not modeled correctly. In this paper our main focus is to estimate the bandwidth of the distributed RLCG interconnects for high speed devices. A closed form solution for bandwidth is obtained by incorporating initial conditions approach for distributed RLCG interconnects for high speed devices.

An accurate crosstalk noise estimation method for two simultaneously switched on-chip VLSI distributed RLCG global interconnects

On-chip inductive effects are becoming predominant in deep submicron (DSM) interconnects due to increasing clock speed, circuit complexity and decreasing interconnect lengths. Inductance causes noise in the signal waveforms, which could adversely affect the performance of the circuit and signal integrity. The traditional analysis of crosstalk in a transmission line begins with a lossless LC representation, yielding a wave equation governing the system response. This paper proposes a difference model approach to derive crosstalk in the transform domain. A closed form solution for crosstalk is obtained by incorporating initial conditions using difference modal approach for distributed RLCG interconnects. We have derived the crosstalk metric for two parallel lines when both are switching simultaneously. A raw evaluation of the crosstalk could be at the origin of a malfunction of the circuit. Cross talk can be analyzed by computing the signal linkage between aggressor or attacker nets and victim nets. The attacker net carries a signal that couples to the victim net through the mutual inductance. In order to determine the effects that this cross talk will have on circuit operation, the resulting voltage expressions at the victim and aggressor must be calculated. This paper proposes a difference model approach for the effective voltages at the victim and aggressor using superposition theorem. The accuracy of our approach is justified by the results obtained from SPICE simulation.

Beta Distribution Based Slew Evaluation Approach for On-Chip RC Interconnects by Using Moment Matching Technique

With the development of technology, as it is scaling towards nanometer regime, for optimizations like physical synthesis and static timing analysis, accurate interconnect delay and slew computation has become critical. The timing verification of digital integrated circuits has become an extremely difficult task due to statistical variations in the gate and wire delays. Statistical timing analysis techniques are being developed to tackle this important problem. The variations of critical dimensions in modern VLSI technologies lead to variability in interconnect performance that must be fully accounted for in timing verification. However, handling a multitude of inter-die/intra-die variations and assessing their impacts on circuit performance can dramatically complicate the timing analysis. So efficient interconnect delay and slew computation has become critical in this era. Slew rate determines the ability of a device to handle the varying signals. Determination of slew rate to a good proximity is very much essential for efficient design of high speed CMOS integrated circuits. This work presents an accurate and efficient model to compute the slew metric of on-chip interconnect of high speed CMOS circuits. Our slew metric assumption is based on the Beta Distribution function. The Beta distribution is used to characterize the normalized homogeneous portion of the step response. For a generalized RC interconnect model, the stability of the Beta Distribution model is guaranteed.

Interconnect Slew Metric Using Nakagami-M Distribution

Slew rate determines the ability of a device to handle the varying signals. Determination of the slew rate to a good proximity is thus essential for efficient design of high speed CMOS integrated circuits. This in turn reduces the output switching surges in the device. Interconnect slew has become a crucial bottleneck for any high density and high speed VLSI circuits. In this paper we have proposed an accurate and efficient model to compute the slew metric of on chip interconnect of high speed CMOS VLSI deigns. Our slew metric is based on the Nakagami-M distribution function. Comparison of simulation results with other established models justifies the accuracy of our slew approach.