Vikas Maheshwari

An Explicit Approach for Delay Evaluation for On-Chip RC Interconnects Using Beta Distribution Function by Moment Matching Technique

As the technology scales down to nanometer regime, interconnect delay is more dominant than gate delay. Many approaches primarily concentrated to find the interconnect delay rather than gate delay so that one can increase the speed of the circuit by simply decreasing the interconnect delay. Several approaches have been proposed to find the interconnect delay accurately and efficiently. By considering the impulse responses of linear circuit as a Probability Distribution Function (PDF), Elmore first estimated the value of interconnect delay. Several approaches have been proposed after Elmore Delay metric like PRIMO, AWE, h-gamma, WED, D2M etc. and are proven to be more accurate than Elmore delay metric. But they suffer from computational complexity when using in total IC design processes. From then onwards many researchers are trying to get a simplified and accurate expressions for interconnect delay by using different techniques and by considering different Probability Distribution Functions (PDF) as their impulse responses. Our work presents a closed form formula for on-chip VLSI RC interconnects delay. Delay metric is obtained by matching circuit moments to the Beta distribution function. The delay metric can be easily implemented for both step and ramp inputs by using a single look-up table. By simply calculating first two circuit moments we can find the interconnect delay of the linear circuit and the computation is also less when compared to other approaches which involve greater computational complexity. As impulse response of the linear circuit matches, in most of the cases, with the Probability Distribution Function (PDF) of Beta Distribution, this method of finding interconnect delay can be used in many linear circuits. The accuracy of our model is justified with the results compared with that of SPICE simulations and the models that have already being proposed with other probability distribution function.

Unified delay analysis for on-chip RLCG interconnects for ramp input using fourth order transfer function

Earlier only the delay caused due to the presence of gates was considered to be an important issue, but now with decreasing feature size and increasing complexity, on-chip interconnect delay has acquired prominence for incremental performance-driven layout synthesis. In this paper, we have obtained an analytical delay model, for RLCG interconnect lines, that in addition to preserving the effectiveness of the previous RLC interconnect models, improves the accuracy for deep submicron technologies that are used at higher frequencies. As the existing works till date, have mostly focused on RC and RLC interconnects with step signal as its input, this approach towards RLCG interconnects is a challenge in itself. In this paper, we have put forward an analytical model, which could accurately capture the on-chip interconnect delay. As we move onto higher frequency ranges, of the order of GHz, the effects of shunt conductance can not be ignored, as that provides a measure of the possible leakage. Due to these reasons, we have derived our on-chip interconnect delay metric considering distributed RLCG segments, rather than sticking to the conventional RLC and RC. The experimental results reveal that our model matches very well with the delay calculations, obtained using SPICE, resulting in an error of less than 4%.

Efficient coupled noise estimation for RLC on-chip interconnect

This paper presents an accurate, fast and simple closed form solution to estimate crosstalk noise between two adjacent wires in VLSI circuits, using RLC interconnect model. Noise analysis and avoidance techniques are critical steps in deep submicron VLSI technology. Currently noise analysis performed either through circuit or timing simulation. These techniques are still inefficient for analyzing massive amount of interconnect data found in present day integrated circuit. This paper presents an efficient technique for estimation of coupled noise in on-chip VLSI interconnects. This noise estimation metric is an upper bound for RLC circuit, being similar in spirit to Elmore delay in timing analysis. Such an efficient noise metric is required especially for noise and physical design based noise avoidance techniques.

Modeling of on-chip global RLCG interconnect delay for step input

In this paper, we begin with the analysis of the signal delay through an ideal RLCG transmission line model, without the driver and the load impedance. This yields to the transform voltage and current equations governing the system response by incorporating appropriate boundary conditions for interconnect delay analysis. Two port parameters in terms of ABCD matrix are obtained. Further, we considered a practical transmission line with driver and load to find the relation between the transform input and output voltage response in s-domain. The relation thus obtained is applied to step input system and the transient response for it in time domain is obtained using inverse Laplace transform. Our main objective is to find the shape function of a wire which minimizes delay for RLCG circuit. Although the problem has been studied under the Elmore delay model, it is only a rough estimate of the actual delay and more accurate estimation of the actual delay should be used to determine the wire shape function. The use of transmission line model in our study gives a very accurate estimate of the actual delay. Previous studies under Elmore delay model suggest that exponential wire shape function to be of the form f(x)=ae−bx by solving the diffusion equation, we derive the transient response in the time domain as a function of a and b for step input. The coefficients a and b are determined so that the actual (50% delay) is minimized. The proposed expressions give a very small error with experimental results (10%–15%).

Accurate estimation of on-chip global RLC interconnect delay for step input

In this paper, firstly, we have calculated the delay through an ideal RLC transmission line model, without the driver and the load impedance. This yields to the transform voltage and current equations governing the system response by incorporating appropriate boundary conditions for interconnect delay analysis. Two port parameters in terms of ABCD matrix are obtained. Further we considered a practical transmission line with driver and load to find the relation between the transform input and output voltage response in s-domain. The relation thus obtained is applied to step input system and the transient response for it in time domain is obtained using inverse Laplace transform. Our main objective is to find the shape function of a wire which minimizes delay for RLC circuit. Although the problem has been studied under the Elmore delay model, it is only a rough estimate of the actual delay and more accurate estimation of the actual delay should be used to determine the wire shape function. The use of transmission line model in our study gives a very accurate estimate of the actual delay. Previous studies under Elmore delay model suggest that exponential wire shape function to be of the form f(x)=ae−bx. By solving the diffusion equation, we derive the transient response in the time domain as a function of a and b for step input. The coefficients a and b are determined so that the actual (50% delay) is minimized.

A Novel Power Estimation Method for On-chip VLSI Distributed RLCG Global Interconnects Using Model Order Reduction Technique

Due to high packaging density of components, power is increasingly becoming the bottleneck for the design of high performance VLSI circuits. It is essential to analyze how the various components of power are likely to scale in the future, thereby identifying the key problematic areas. This is an important fact because the conventional design, analysis, and synthesis of VLSI circuits are based on the assumption that gates are the main sources of on-chip power consumption. While most analysis focus on the timing aspects of interconnects, power consumption is also important. In this paper, the power distribution estimation of interconnects is studied using a reduced-order model. The relation between power consumption and the poles and residues of a transfer function is derived, and an appropriate driver model is developed, allowing power consumption to be computed efficiently. At higher frequency of operations, of the order of few GHz, the interconnect is to be analyzed with a distributed RLCG model. Because at very high frequency, the dielectric material deviates from it’s ideal nature. This gives rise to the shunt conductance matrices. In this paper we have considered the high frequency effects and modeled the interconnect as distributed RLCG segments to compute the interconnect power dissipation. The results obtained from SPICE simulation justify the accuracy of our model.

Power-Estimation for on-Chip VLSI Distributed RLC Global Interconnect using Model Order Reduction Technique

ABSTRACT Power is increasingly becoming the bottleneck for the design of high performance VLSI circuits. It is essential to analyze how the various components of power are likely to scale in the future, thereby identifying the key problematic areas. While most analyses focus on the timing aspects of interconnects, power consumption is also important. In this paper, the power distribution estimation of interconnects is studied using a reduced-order model [1]. The relation between power consumption and the poles and residues of a transfer function is derived, and an appropriate driver model is developed, allowing power consumption to be computed efficiently. Categories and Subject Descriptors B.7.2 [ Integrated Circuits ]: Design Aids – Simulation; General Terms Algorithms, Design, Theory Keywords Power estimation, Model Order Reduction, RCL Interconnect, Moment matching 1. INTRODUCTION As the scale of process technologies steadily shrinks and the size of designs increases, interconnects have increasing impact on the area, delay, and power consumption of circuits. Over the past decade there have been a number of advances in modeling and the analysis of interconnect that have facilitated the continual advances in design automation for systems of increasing size and frequency. As integrated circuit feature sizes continue to scale well below 0.18 µm [2], active device counts are reaching hundreds of millions. Interconnect models must incorporate distributed self and mutual inductance to accurately estimate time delay and crosstalk in a multilevel network for multi-GHz gigascale integration (GSI) [3]. In addition to interconnect delay, crosstalk noise resulting from capacitive and, more recently investigated, inductive effects [4], [5] between adjacent interconnect lines is also becoming a primary concern for ICs performance and reliability. Furthermore, with present VLSI technology, on -chip interconnects are best modeled as a network of coupled lines the amount of interconnect among the devices tends to grow super linearly with the transistor counts, and the chip area is often limited by the physical interconnect area. Due to these interconnect area limitations, the interconnect dimensions are scaled with the devices whenever possible. In addition, to provide more wiring resources, IC’s now accommodate numerous metallization layers, with more to come in the future. These advances in technology that result in scaled, multi-level interconnects may address the wire ability problem, but in the process create problems with signal integrity and interconnect delay. As regards power, the situation is similar in that the portion of power associated with interconnects is increasing. This is an important fact because the conventional design, analysis, and synthesis of VLSI circuits are based on the assumption that gates are the main sources of on-chip power consumption. Furthermore, the power consumed by interconnects results in a phenomenon, called self heating, which reduces electro-migration induced mean time to failure (MTF) [6]. It is shown in [7] that the power distribution analysis on interconnects is feasible in frequency domain using poles and residues. However, high complexity is inevitable when calculating the power dissipation of the whole interconnects since poles and residues of the current flowing through each element have to be calculated. As feature sizes are decreased to deep sub-micrometer dimensions, on-chip interconnect is best modeled as a distributed RLC line. However, unlike the RC model, such a model increases the complexity of interconnects crosstalk noise and its induced delay estimation. Advances in deep sub-micron technology indicate that present and future interconnects might no longer be considered as simply made of RC lines. Thus, RLC interconnect models become a necessity [8]. It therefore appears that, if accurate interconnect delay estimation is to be achieved, modeling interconnect as a distributed RLC line is necessary. In this case, the commonly and generally well-accepted Elmore delay calculation becomes inapplicable to RLC interconnect networks due to their non-monotonic characteristics induced by inductances [8] [9]. To verify the effects induced by interconnects a combination of extraction and analysis is necessary. Extraction determines the capacitance and the resistance of interconnects, which can then be used to build a circuit model for the analysis of interconnect effects. For analysis (or estimation), extensive studies have been made of the use of model order reduction over the last few years, following the introduction of AWE [9]. Model order reduction is based on approximating the Laplace-domain transfer function of a linear network by a relatively small number of dominant poles and zeros. Such reduced order models can be used to predict the timedomain or frequency-domain response of the linear network. Power, which inherently involves improper integration, can be derived from the poles and residues of the transfer function, which requires only algebraic computation. When the interconnect is driven by MOSFETs and connected to the gates of MOSFETs, the

Crosstalk aware bandwidth modeling for distributed on-chip RLCG interconnects using difference model approach

In case of very high frequency as in Giga-scale (GHz), no longer can interconnects be treated as mere delays or lumped RC networks. The most common simulation model for interconnects is the distributed RC and RLC model. The impact of interconnects on circuit performance in both the analog and digital domains is ever increasing. Unfortunately, this model has many limitations which can lead to inaccurate simulations if not modeled correctly. Crosstalk, ringing and reflection are just some of the issues that need to be addressed and then circumvented or utilized. The traditional analysis of crosstalk in a transmission line begins with a lossless LC representation, yielding a wave equation governing the system response. With the reduction of distances between wires in deep sub-micron technologies, coupling capacitances are becoming significant. This increase in capacitance gives rise to noise which is capable of propagating a logical fault. A bad evaluation of the crosstalk could be at the origin of a malfunction of the circuit. Cross talk can be analyzed by computing the signal linkage between aggressor or attacker nets and victim nets. The attacker net carries a signal that couples to the victim net through the parasitic capacitance. To determine the effects that this cross talk will have on circuit operation, the resulting delays and logic levels for the victim nets must be computed. This paper proposes a difference model approach to derive a crosstalk aware bandwidth estimation method in the transform domain. A closed form solution for bandwidth is obtained by incorporating initial conditions using difference model approach for distributed RLCG interconnects. The simulation results justify the accuracy of our approach.

Closed Form Bandwidth Expression for Distributed On-chip RLCG Interconnects

With the increasing levels of on-chip integration, more functional units are integrated onto a single die, the logic delays decrease due to faster transistors. At the same time, local interconnect delays similarly improve because the physical size of circuit blocks decrease, and the local interconnect spans shorter distances. During the interconnect design process, multiple design criteria are considered, such as delay, power, bandwidth, and noise. Performance of any high speed VLSI circuit depends on the bandwidth as it decreases with increase in the length of interconnects. The impact of interconnects on circuit performance in both the analog and digital domains is ever increasing. In case of very high frequency as in Gigascale (GHz), no longer can interconnects be treated as mere delays or lumped RC networks. The most common simulation model for interconnects is the distributed RLC model. Unfortunately, this model has many limitations which can lead to inaccurate simulations if not modeled correctly. In this paper our main focus is to estimate the bandwidth of the distributed RLCG interconnects for high speed devices. A closed form solution for bandwidth is obtained by incorporating initial conditions approach for distributed RLCG interconnects for high speed devices.

Wave propagation based analytical delay and cross talk noise model for distributed on-chip RLCG interconnects

This paper proposes a wave propagation based approach to derive crosstalk and delay between two coupled RLCG interconnects in the transform domain. The increase of clock frequency into the GHz range, coupled with longer length interconnects of small cross-section and low dielectric strength, can result in cross coupling effects between on-chip interconnects. The traditional analysis of crosstalk in a transmission line begins with a lossless LC representation, yielding a wave equation governing the system response. In order to determine the effects that this cross talk will have on circuit operation, the resulting delays and logic levels for the victim nets must be computed. In this paper, we propose four reflection wave propagation based analytical model for estimation of crosstalk. An emphasis was made on the distributed nature of the RLCG model, thus underlining the effect of parasitic coupling inductance and conductance on present and future on-chip interconnects.