A. Kluge

A pixel front-end ASIC in 0.13 μm CMOS for the NA62 experiment with on pixel 100 ps Time-to-Digital Converter

The paper describes the design of a front-end chip for hybrid pixel detectors optimized for good timing resolution (200 ps rms) and high event rate (150 kHz per pixel). Each channel consists of a fast transimpedance amplifier with 5 ns peaking time, a constant fraction discriminator (CFD), and a Time-to-Digital Converter (TDC). In order to cope with the rate requirement, a multi-event buffering scheme employing both analog and digital pipelines is implemented in each cell. This development is part of the R&D activity for the silicon tracker of the NA62 experiment at CERN. The architecture of the chip and the design of the critical building blocks are discussed in the paper.

R&D Paths of Pixel Detectors for Vertex Tracking and Radiation Imaging

This report reviews current trends in the R&D of semiconductor pixellated sensors for vertex tracking and radiation imaging. It identifies requirements of future HEP experiments at colliders, needed technological breakthroughs and highlights the relation to radiation detection and imaging applications in other fields of science.

The ALICE Silicon Pixel Detector: readiness for the first proton beam

The Silicon Pixel Detector (SPD) is the innermost element of the ALICE Inner Tracking System (ITS). The SPD consists of two barrel layers of hybrid silicon pixels surrounding the beam pipe with a total of ≈ 107 pixel cells. The SPD features a very low material budget, a 99.9% efficient bidimensional digital response, a 12 μm spatial precision in the bending plane (r) and a prompt signal as input to the L0 trigger. The SPD commissioning in the ALICE experimental area is well advanced and it includes calibration runs with internal pulse and cosmic ray runs. In this contribution the commissioning of the SPD is reviewed and the first results from runs with cosmic rays and circulating proton beams are presented.

Experimental results from a pixel front-end for the NA62 experiment with on pixel constant fraction discriminator and 100 ps Time to Digital Converter

The paper presents test results of a front-end ASIC developed for fast timing applications with silicon pixel detectors. Implemented in a 0.13 μm CMOS process, the prototype integrates 107 read-out cells. In an area of 300 μm × 300 μm each cell incorporates a fast transimpedance amplifier with 3 ns peaking time, a Constant Fraction Discriminator (CFD) and a Time to Digital Converter (TDC). The analog front-end is optimized for signals from 1 fC to 10 fC and dissipates lmW from a 1.2 V supply. Electrical tests of the key building blocks and system level aspects are discussed in the paper.

Development of the ASICs for the NA62 pixel gigatracker

We present the ASIC development for the readout electronics of the Gigatracker pixel detector of NA62. Specifications of this detector are challenging in terms of timing precision with a hit time stamp accuracy of 100 ps and a peak hit rate of 50 Mhits/cm/s. A timing precision and hit rate are more than one order of magnitude faster than pixel LHC readout ASIC. The research for pixel cell design and the readout architectures are following two approaches, which are presented and discussed in this paper. Presently demonstrator prototypes are under development and SPICE simulation results of the frontend, the readout strategy and and the pixelcolumn are also presented and discussed.

Pixel read-out architectures for the NA62 gigatracker

Beam particles in NA62 experiment are measured with a Si-pixel sensor having a size of 300 μm x 300 μm and a time resolution of 150 ps (rms). To meet the timing requirement an adequate strategy to compensate the discriminator time-walk must be implemented and an R&D effort investigating two different options is ongoing. In this presentation we describe the two different approaches. One is based on the use of a constant-fraction discriminator followed by an on-pixel TDC. The other one is based on the use of a Time-over-Threshold circuit followed by a TDC shared by a group of pixels. The global architectures of both the front-end ASIC will be discussed. I. THE GIGATRACKER SYSTEM The aim of the proposed NA62 experiment at the CERN SPS is to study the very rare decay of the charged K meson into a pion and neutrino-antineutrino pair. One of the key components of NA62 will be the GigaTracker, which consists of three matrices of Si-pixel stations, each covering a sensitive area of 60 mm x 27 mm. Each pixel is 300 μm x 300 μm [1]. The GigaTracker is designed to measure the beam particle trajectory with a space resolution of 100 μm (rms) and a timing accuracy of 150 ps (rms). In order to reconstruct the momentum of the beam particles a system of four dipoles, A1...A4 in Fig.1, provides the momentum selection followed by the beam recombination. The timing resolution of 150 ps (rms) is an unusual requirement for a traditional pixel detector and none of the existing systems has such a capability. Other challenging aspects are due to the high radiation operational environment and the very low material budget restraint (0.5% X0 per station, sensor thickness 200 μm, read-out chip thickness 150 μm). Figure 1: GigaTracker system Each silicon sensor will be read-out by 10 front-end ASICs, with 45x40 read-out cells each. The 10 read-out chips will be bump-bonded to the pixels, so only one side of the chip will be used for external connections (wire bonding pads in Fig. 2). Figure 2: Sensor and read-out chips The particle rate, which is higher in the central part of the sensor, is estimated to be ~1.5 MHz/mm maximum, which corresponds to 130 MHz per chip and 140 kHz per

The silicon pixel detector (SPD) for the ALICE experiment

The ALICE silicon pixel detector (SPD) constitutes the two innermost layers of the inner tracking system (ITS). The basic building block of the SPD is the half-stave carrying two detector ladders. The half-stave is equipped with a multi-chip module (MCM) and an optical fibre link for control and readout. A 5-layer aluminium/polyimide bus ensures the distribution of power and signals on each half-stave. The half-staves are mounted on a light-weight carbon-fibre structure with an integrated evaporative cooling system. An overview of the SPD development and the current status of the construction are presented.

The electro-mechanical integration of the NA62 GigaTracker time tagging pixel detector

The NA62 GigaTracker is a low mass time tagging hybrid pixel detector operating in a beam with a particle rate of 750 MHz. It consists of three stations with a sensor size of 60 x 27mm(2) containing 18000 pixels, each 300 x 300 mu m(2). The active area is connected to a matrix of 2 x 5 pixel ASICs, which time tag the arrival of the particles with a binning of 100 ps. The detector operates in vacuum at -20 to 0 degrees C and the material budget per station must be below 0.5% X-0. Due to the high radiation environment of 2 x 10(14) 1 MeV neutron equivalent cm(-2)/yr(-1) it is planned to exchange the detector modules regularly. The low material budget, cooling requirements and the request for easy module access has driven the electro-mechanical integration of the GigaTracker, which is presented in this paper.

The 5ns peaking time transimpedance front end amplifier for the silicon pixel detector in the NA62 Gigatracker

We present the design and test results of a front-end prototype circuit developed in 130 nm CMOS technology for the readout of the Gigatracker pixel detector experiment in NA62 at CERN. The main challenges for the front end amplifier are very high signal hit rate (dead time less than 100ns, average signal rate 100 kHz) and 100 ps timing resolution combined with the level of affordable power consumption (< 2W/cm2) and noise (< 200 e−ENC). The predicted ENC levels for the nominal detector capacitance of 250 fF and maximum leakage current of the order of 20 nA are below 200 e−. The overall power consumed by the analogue and digital part of the pixel cell is in the order of 130 μW. The optimization of the design as well as test results of the prototype front end chip are evaluated and discussed.

Test-beam results of a silicon pixel detector with Time-over-Threshold read-out having ultra-precise time resolution

A time-tagging hybrid silicon pixel detector developed for beam tracking in the NA62 experiment has been tested in a dedicated test-beam at CERN with 10 GeV/c hadrons. Measurements include time resolution, detection efficiency and charge sharing between pixels, as well as effects due to bias voltage variations. A time resolution of less than 150 ps has been measured with a 200 μm thick silicon sensor, using an on-pixel amplifier-discriminator and an end-of-column DLL-based time-to-digital converter.