A. Kugel

Correlation analysis on GPU systems using NVIDIA's CUDA

Functional magnetic resonance imaging allows non-invasive measurements of brain dynamics and has already been used for neurofeedback experiments, which relies on real time data processing. The limited computational resources that are typically available for this have hindered the use of connectivity analysis in this context. A basic, but already computationally demanding analysis method of neural connectivity is correlation analysis that computes all pairwise correlations coefficients between the measured time series. The parallel nature of the problem predestines it for an implementation on massive parallel architectures as realized by GPUs and FPGAs. We show what performance benefits can be achieved when compared with current desktop CPUs. The use of correlation analysis is not limited to brain research, but is also relevant in other fields of image processing, e.g. for the analysis of video streams.

The base-line DataFlow system of the ATLAS trigger and DAQ

The base-line design and implementation of the ATLAS DAQ DataFlow system is described. The main components of the DataFlow system, their interactions, bandwidths, and rates are discussed and performance measurements on a 10% scale prototype for the final ATLAS TDAQ DataFlow system are presented. This prototype is a combination of custom design components and of multithreaded software applications implemented in C++ and running in a Linux environment on commercially available PCs interconnected by a fully switched gigabit Ethernet network.

The MPRACE framework: An open source stack for communication with custom FPGA-based accelerators

We present an open source stack for the development of custom FPGA boards, primarily but not limited to PCI Express interconnects. Supporting current Linux distributions, the stack consists of a PCI driver, an IP core for a DMA engine, a hardware abstraction library for IO operations, and a buffer management library for efficient handling of data transfers between an application and a FPGA design. The stack has been validated in diverse hardware and software platforms and provides several building blocks that facilitate the use of accelerators in applications. The DMA Engine IP provides high performance data transfers in PCIe 4-lane boards with Xilinx PCIe cores, with 380 MB/s read and 700 MB/s write maximum measured performance. The buffer management library allows the utilization of 80–95% of this bandwidth with reduced resource consumption and minimal effort.

Large format X-ray imager with mega-frame readout capability for XFEL, based on the DEPFET active pixel sensor

We propose a new detector system capable to fulfil the requirements of the future XFEL in Hamburg. The instrument will be able to record X-ray images with a maximum frame rate of 5MHz and to achieve a high dynamic range. The system is based on a pixel-silicon sensor with a new designed non-linear-DEPFET as a central amplifier structure. The detector chip is bump-bonded to a set of mixed signal readout ASICs that provide full parallel readout. The signals coming from the detector, after having been processed by an analog filter, are immediately digitized by a series of 8-ENOB ADCs and locally stored in a custom designed memory also integrated in the ASICs designed in the 130nm CMOS technology. During the time gap of 99ms of the XFEL machine, the digital data are sent off the focal plane to a DAQ electronics that acts as an interface to the back-end of the whole instrument. The pixel sensor has been designed so as to combine high energy resolution at low signal charge with high dynamic range. This has been motivated by the desire to be able to be sensitive to single low energy photons and, at the same time, to measure at other positions of the detector signals corresponding to up to 104 photons of 1keV. In order to fit this dynamic range into a reasonable output signal swing, achieving at the same time single photon resolution, a strongly non linear characteristics is required. The new proposed DEPFET provides the required dynamic range compression at the sensor level, considerably facilitating the task of the electronics. At the same time the DEPFET charge handling capacitance is enormously increased with respect to standard DEPFETs. The Pixel matrix will have a format of 1024×1024 with a pixel size of 200×200 µm2.

Performance of the final Event Builder for the ATLAS Experiment

Event data from proton-proton collisions at the LHC will be selected by the ATLAS experiment in a three level trigger system, which reduces the initial bunch crossing rate of 40 MHz at its first two trigger levels (LVL1+LVL2) to ~3 kHz. At this rate the Event-Builder collects the data from all read-out system PCs (ROSs) and provides fully assembled events to the the event-filter (EF), which is the third level trigger, to achieve a further rate reduction to ~ 200 Hz for permanent storage. The event-builder is based on a farm of O(100) PCs, interconnected via gigabit Ethernet to O(150) ROSs. These PCs run Linux and multi-threaded software applications implemented in C++. All the ROSs and one third of the event-builder PCs are already installed and commissioned. We report on performance tests on this initial system, which show promising results to reach the final data throughput required for the ATLAS experiment.

ATLAS trigger/DAQ RobIn prototype

A Toroidal LHC ApparatuS (ATLAS) Trigger/Data Acquisition (TDAQ) system connects via 1600 Read-Out-Links (ROL) to the ATLAS subdetectors. Each Read-Out-Buffer (RobIn) prototype attaches to 2 ROLs, buffers the incoming event data stream of 160 MB/s each, and provides samples upon request to the TDAQ system. We present the design of the PCI-based RobIn module, which is built around a XILINX XV2V1500 field-programmable-gate-array, together with initial results from rapid prototyping studies.

The IBL readout system

The first upgrade for the ATLAS Pixel Detector will be an additional layer, which is called IBL (Insertable B-Layer). To readout this new layer, built from new electronics, an update of the readout electronics is necessary. The aim is to develop a system which is capable to read out at a higher bandwidth, but also compatible with the existing system to be integrated into it. This paper describes the necessary development to reach a new readout system, concentrating on the requirements of a newly designed Back of Crate card as the optical interface in the counting room.

Proposal for a readout driver card for the ATLAS Insertable B-Layer

An additional inner layer for the existing ATLAS Pixel Detector, called Insertable B-Layer (IBL), is under design and it will be installed by Phase I. New front-end readout ASICs fabrication (FE-I4) will replace the previous chips in this layer. The new system features higher readout speed — 160Mb/s per ASIC — and simplified control. The current data acquisition chains are composed of front-end and readout chips, Back-Of-Crate (BOCs) cards and ReadOut Driver cards (RODs). This paper presents a proposal for the new ROD board, which implements modern FPGAs and high-speed links with the detector and with the ATLAS TDAQ system.

The C-RORC PCIe card and its application in the ALICE and ATLAS experiments

The ALICE and ATLAS DAQ systems read out detector data via point-to-point serial links into custom hardware modules, the ALICE RORC and ATLAS ROBIN. To meet the increase in operational requirements both experiments are replacing their respective modules with a new common module, the C-RORC. This card, developed by ALICE, implements a PCIe Gen 2 x8 interface and interfaces to twelve optical links via three QSFP transceivers. This paper presents the design of the C-RORC, its performance and its application in the ALICE and ATLAS experiments.

A PowerPC-based control system for the Read-Out-Driver module of the ATLAS IBL

The ATLAS experiment at LHC planned to upgrade the existing Pixel Detector with the insertion of an innermost silicon layer, called Insertable B-layer (IBL). A new front-end ASIC has been foreseen (named FE-I4) and it will be read out with improved off-detector electronics. In particular, the new Read-Out Driver card (ROD) is a VME-based board designed to process a four-fold data throughput. Moreover, the ROD hosts the electronics devoted to control operations whose main tasks are providing setup busses to access configuration registers on several FPGAs, receiving configuration data from external PCs, managing triggers and running calibration procedures. In parallel with a backward-compatible solution with a Digital Signal Processor (DSP), a new ROD control circuitry with a PowerPC embedded into an FPGA has been implemented. In this paper the status of the PowerPC-based control system will be outlined with major focus on firmware and software development strategies.