N. Schroer

The IBL readout system

The first upgrade for the ATLAS Pixel Detector will be an additional layer, which is called IBL (Insertable B-Layer). To readout this new layer, built from new electronics, an update of the readout electronics is necessary. The aim is to develop a system which is capable to read out at a higher bandwidth, but also compatible with the existing system to be integrated into it. This paper describes the necessary development to reach a new readout system, concentrating on the requirements of a newly designed Back of Crate card as the optical interface in the counting room.

Proposal for a readout driver card for the ATLAS Insertable B-Layer

An additional inner layer for the existing ATLAS Pixel Detector, called Insertable B-Layer (IBL), is under design and it will be installed by Phase I. New front-end readout ASICs fabrication (FE-I4) will replace the previous chips in this layer. The new system features higher readout speed — 160Mb/s per ASIC — and simplified control. The current data acquisition chains are composed of front-end and readout chips, Back-Of-Crate (BOCs) cards and ReadOut Driver cards (RODs). This paper presents a proposal for the new ROD board, which implements modern FPGAs and high-speed links with the detector and with the ATLAS TDAQ system.

A PowerPC-based control system for the Read-Out-Driver module of the ATLAS IBL

The ATLAS experiment at LHC planned to upgrade the existing Pixel Detector with the insertion of an innermost silicon layer, called Insertable B-layer (IBL). A new front-end ASIC has been foreseen (named FE-I4) and it will be read out with improved off-detector electronics. In particular, the new Read-Out Driver card (ROD) is a VME-based board designed to process a four-fold data throughput. Moreover, the ROD hosts the electronics devoted to control operations whose main tasks are providing setup busses to access configuration registers on several FPGAs, receiving configuration data from external PCs, managing triggers and running calibration procedures. In parallel with a backward-compatible solution with a Digital Signal Processor (DSP), a new ROD control circuitry with a PowerPC embedded into an FPGA has been implemented. In this paper the status of the PowerPC-based control system will be outlined with major focus on firmware and software development strategies.

ATLAS IBL: integration of new HW/SW readout features for the additional layer of Pixel Detector

An additional inner layer for the existing ATLAS Pixel Detector, called Insertable B-Layer (IBL), is under design. The front-end electronics features a new readout ASIC, named FE-I4, which requires new off-detector electronics, currently realized with two VME-based boards: the Back Of Crate module (BOC) implements optical I/O functionality and the ReadOut Driver module (ROD) implements data processing functionality, plus a Timing Interface Module (TIM). This paper presents a proposal for the IBL readout system, mainly focusing on the ROD board.

ATLAS IBL BOC prototype evaluation

The Pixel Detector of the ATLAS experiment at CERN will be upgraded with an Insertable B-Layer (IBL) in 2013. For this fourth and innermost layer 448 newly developed pixel sensor readout chips (FE-I4) are used which will provide data from about 12 million pixel. For the readout of these chips new off-detector electronic components are needed as the FE-I4s feature an increased readout bandwidth which can not be handled by the current system. To provide a degree of backward compatibility the new system will keep the structure of VME card pairs: The back of crate card (BOC) establishes the optical interfaces to the detector front end as well as to the read out system (ROS) while the read out driver (ROD) manages data processing and calibration. Both cards, the BOC and the ROD, have been redesigned and feature modern FPGA technology, yielding an integration four times higher than the current system. This paper will describe the concept of hard- and firmware of the new IBL BOC and present results of the testing with the first prototypes.

The ATLAS IBL BOC Demonstrator

The Insertable-B-Layer (IBL) is a new pixel detector layer to be installed at the ATLAS experiment at the LHC, CERN in 2013. It will be integrated into the general pixel readout and software framework, hence the off-detector readout electronics has to support the new front-end electronics whilst maintaining a high degree of interoperability to the components of the existing system. The off-detector readout is realised using a number of VME card pairs ROD and BOC plus a VME crate controller and a custom timing distribution system. The main elements of the new BOC design comprise optical interfaces towards the detector, signal conditioning and data recovery logic. We present the demonstrator used to verify the design approach. The demonstrator is based on a XILINX SP605 FPGA evaluation board and uses a Microblaze processor inside the FPGA to provide easy and flexible access to all essential BOC functions and the corresponding emulator modules, which enable full test of the entire BOC functionality even without any external components. However, optical interfaces may be connected via a mezzanine card. We present the details of the emulation circuitries together with measurement results showing the operation of the BOC logic.

The ATLAS IBL BOC prototype

The Pixel Detector of the ATLAS experiment at CERN will be upgraded with an Insertable B-Layer (IBL) in 2013. To handle the data readout the currently used VME card pairs consisting of a back of crate card (BOC) and a read out driver (ROD) are being redesigned. This paper presents details of the hardware design of the new BOC prototype, which takes advantage from modern FPGA technology and commercial optical modules and abandons the need for a variety of custom components used on the old card. Also the throughput is four times higher and additional features are implemented.