A.L. Lacaita

Electronic switching effect and phase-change transition in chalcogenide materials

The threshold switching mechanism in amorphous chalcogenides is investigated, showing experimental data that once and for all demonstrate its electronic nature. The physical mechanisms responsible for the switching to the highly conductive state are discussed and the impact of cumulative read-out pulses is also investigated, showing that phase-change transitions induced by usual reading operations in phase-change memory cells are completely negligible.

Evidence for threshold switching in the set process of NiO-based RRAM and physical modeling for set, reset, retention and disturb prediction

This work addresses the set and reset mechanisms in NiO-based resistive-switching memory (RRAM) devices, presenting a new physics-based model for RRAM reliability and programming. We show experimental evidence that the set process is initiated by threshold switching, that is a reversible electronic transition to a high conductance state. We develop set/reset models for prediction of programming voltage and time under sweep or pulsed conditions. The speed limitations of RRAMs are then assessed by a detailed study of reset operation in the pulsed regime, showing evidence for over-reset under high-voltage, fast programming conditions (< 1 mus).

How far will silicon nanocrystals push the scaling limits of NVMs technologies

For the first time, memory devices with optimized high density (2E12#/cm/sup 2/) LPCVD Si nanocrystals have been reproducibly achieved and studied on an extensive statistical basis (from single cell up to 1 Mb test-array) under different programming conditions. An original experimental and theoretical analysis of the threshold voltage shift distribution shows that Si nanocrystals have serious potential to push the scaling of NOR and NAND flash at least to the 35 nm and 65 nm nodes, respectively.

Scaling trends for random telegraph noise in deca-nanometer Flash memories

We present a thorough investigation of the random telegraph noise scaling trend for both NAND and NOR floating-gate flash memories, including experimental and physics-based modeling results. The statistical distribution of the random telegraph noise amplitude is computed using conventional 3D TCAD simulations, establishing a direct connection with cell parameters. The analysis results in a simple formula for the random telegraph noise amplitude standard deviation as a function of cell width, length, substrate doping, tunnel oxide thickness and drain bias. All the simulation results are in good agreement with experimental data and are of utmost importance to understand the random telegraph noise instability and to control it in the development of next generation flash technologies.

On the correlation between surface roughness and inversion layer mobility in Si-MOSFETs

A quantitative analysis of the Si/SiO/sub 2/ interface roughness based on atomic force microscope (AFM) and mobility measurements is presented. Our results show that the spatial components of the roughness affecting the carrier transport lie outside the range probed by AFM, thus making questionable the validity of previously published correlations between AFM measurements and carrier mobility. Based on a numerical model of the roughness scattering, a new physically-based correlation is proposed, highlighting the impact, so far overlooked, of the roughness correlation length on the carrier mobility.

Statistical modeling of reliability and scaling projections for flash memories

A new physically-based model for reliability analysis of flash memories is presented. The model provides a quantitative description of the distribution of the stress-induced leakage current (SILC) in large memory arrays, considering the statistics of the defects responsible for the trap-assisted tunneling (TAT) current. Simulation results are in good agreement with SILC statistics over oxide thicknesses of 6.5, 8.8 and 9.7 nm. The model can be used to quantitatively evaluate the failure rate under different conditions and assess the trade-off between oxide thinning and device reliability. The relationship between tunnel oxide scalability and defect concentration is also quantitatively assessed.

Transient effects of delay, switching and recovery in phase change memory (PCM) devices

Threshold switching effects play a critical role in phase change memory (PCM) devices, since they contribute to the programming (set/reset) times and may lead to unwanted disturbs during the read operation. This work presents a detailed characterization and modeling of transient effects of delay, switching and recovery in PCM devices, allowing to quantitatively evaluate the statistical impact of read disturb and the ultimate speed limitations to set/reset and program/verify loops.

Program/erase dynamics and channel conduction in nanocrystal memories

We present new models for nanocrystal (NC) memories, addressing program/erase (P/E) transients and carrier conduction in the channel controlled by discrete nodes. The model allows for the calculation of the achievable threshold-voltage (V/sub T/) window and P/E times under uniform tunneling-injection conditions. Comparisons with experimental data are shown, demonstrating that our physically-based model correctly captures the VT dependence on critical cell and bias parameters. The model can be used to draw technological guidelines for window optimization in NC cells.

A new channel percolation model for V/sub T/ shift in discrete-trap memories

In this work we studied the mechanisms for channel conduction in discrete-trap memories (DTMs). It is shown that the threshold voltage V/sub T/ in the cell corresponds to a percolation condition in the channel, where the inverted layers connect source to drain. A numerical model is presented which is able to calculate the local profile of V/sub T/ in the channel, and to evaluate the global V/sub T/ in the cell according to a channel percolation condition. The model is shown to account for the size dependence of V/sub T/ in DTM cells, and for the staircase charge-loss characteristics observed on ultrascaled devices. The implications of the percolation mechanism from the reliability point of view are finally discussed in details.

New technique for fast characterization of SILC distribution in flash arrays

A new method for characterizing the SILC in flash memories is presented. The role of the SILC distribution in determining the failure statistics of flash cell arrays is first pointed out. The new technique is then explained, and results from a test array are shown. The description in terms of a simplified formula for the leakage current provides evidence for the bimodal distribution of the SILC distribution in the memory array under test. The bimodal character of the SILC distribution is finally verified by directly comparing characteristics measured on real cells with results of the new method on the same memory chip.