A. Lloris

CMOS current-mode multivalued PLAs

A programmable logic array (PLA) structure for implementation of multivalued combinational and sequential systems is proposed. The PLA is integrable by using a conventional CMOS process and makes a NOR/TSUM two-level implementation of multivalued functions, which can consume less silicon area than an equivalent binary implementation. Pseudo-nMOS and dynamic CMOS implementations for the proposed PLA are also presented, using current-mode inputs and outputs. Since these PLAs operate with several current levels, a significant saving in silicon area can be obtained in comparison with binary PLAs. A four-valued PLA prototype was manufactured using an ordinary CMOS process. Experimental data for this prototype show that the chip operates correctly without significant deterioration in the current levels.

Using decision trees for the minimization of multiple-valued functions

This paper presents a simple procedure for the approximate minimization of multiple-valued functions using multiple-valued decision trees. The proposed procedure is compared with a near-absolute procedure, using for the test four-valued functions of four variables. The results show a great advantage for our procedure with respect to the CPU time needed.

Generalized Hopfield neural network for concurrent testing

The use of generalized Hopfield neural networks in designing the checking circuitry of a concurrent testable circuit is discussed. The aliasing probability, a measure for evaluating the performance of the checking circuitry, is provided. It is shown how, by using spectral techniques based on the Reed-Muller transform, the aliasing probability can be expressed as a function of the Reed-Muller coefficients. Therefore, obtaining the checking circuitry means selecting a set of Reed-Muller spectral coefficients, with fewer elements than a given bound, that minimizes the aliasing probability. To apply the neural networks to design the checking circuitry for concurrent testing, the aliasing probability has been used as an energy function, and the Hopfield neural network has been modified to have an associated energy function with any type of polynomial dependence on the processor states. >

Some improvements in the implementation of multithreshold and multivalued I2.L circuits

After a brief analysis of some problems that arise in the implementation of multi-threshold and multivalued I2L circuits, a global solution for these problems is proposed based on a proper dimensioning of the current mirrors. This solution implies an adequate design of the circuit layout, but the manufacturing process can be the same as for the binary I2L circuits. The problems posed and its practical solutions are checked by simulation with SPICE2 of two circuits: a comparator circuit to detect three current thresholds, and a new 4-bits adder with lookahead carry.

Design of active circuits with non-linear transfer characteristics

A general procedure is presented for the synthesis of active circuits with one-input/ one-output transfer characteristics arbitrarily fixed. The Fortran program that implements this procedure is outlined. The process starts by fitting the curve to be simulated to a piecewise-linear approximation using the least-squares method. Then, the circuit whose transfer characteristic is the piece wise-approximation is calculated. This circuit has two operational amplifiers, working as inverting amplifiers. The program uses as input data only the definition of the function by N points and automatically obtains the breakpoints, the parameters of the straight lines and the mean error of the piecewise-linear approximation, and the parameters of the circuit that synthesizes the function.

Implementation of the unary operators in ternary logic : A universal CMOS circuit

A universal CMOS circuit for the implementation of the unary operators in ternary logic is presented. This circuit supplies simultaneously 12 of the 27 unary operators and, modifying its external connections, it is able to implement, all the unary operators. Further, this circuit includes only MOSFETs (So there is no resistance in its structure), its power dissipation is low and its switching times are standard. For the construction of this circuit, only easily obtainable chips are used.

Universal built-in self-test procedure for CMOS PLA's

The authors present a built-in self-test (BIST) programmable logic array (PLA) design in CMOS technology that provides a high percentage of coverage for multiple stuck-at, crosspoint, and bridging faults and, furthermore detects all simple stuck-open faults in the AND and OR planes and all multiple stuck-open faults in the AND plane. As the test patterns used are the same for all PLAs, a universal test for PLAs is defined. The hardware overhead complexity for this scheme resembles that of previous proposals, although the number of different test patterns used has been reduced. >

Implementation and applications of multivalued decoders

A synthesis procedure is described for multivalued threshold decoders and their application to the implementation of multivalued functions. This method is based on the definition of inversion and extreme functions. Decoders are obtained using only the very simple blocks which synthesize inversion functions. This general design procedure may be used for any integrated circuit technology. As an example, the method is applied to the synthesis of an integrated CMOS quaternary decoder. Both the layout and the timing of the integrated circuit, and their application to the synthesis of multivalued functions and multistable memory elements, are shown.

Analysis of multivalued combinational logic networks with uncertainty

Abstract The paper presents a procedure for the analysis of uncertainty in multivalued combinational logic networks. The external inputs are presumed to be well defined and uncertainty, to be due only to the behaviour of the network. This, method allows us to establish how the uncertainty in the behaviour of some elements of the network affects the behaviour of the whole network. More specifically, given the designation matrix of each element of the network, we obtain the designation matrix for the whole network.

Multithreshold logic circuits implemented with operational amplifiers

ABSTRACT The paper presents a procedure for the synthesis or multithreshold circuits with up to four thresholds. The circuit has three operational amplifiers as its kernel. Given the weight-threshold vector of the boolean function which has to be obtained, the values of the different elements of the circuit are easily obtained. Noise immunity has been computed and has an acceptable value. One example of synthesis is included.