A. Mihaila

Thick silicon membrane technology for reliable and high performance operation of high voltage LIGBTs in Power ICs

A step change in performance and reliability of thick SOI membrane devices compared to earlier generation of devices on ultra-thin SOI membranes is reported in here. The membrane concept first reported offered a landmark improvement in the trade-off between switching losses and breakdown capability (in excess of 700V) but its current capability was limited by the thickness of the silicon membrane (around 30 A/cm2 for LIGBTs on 0.25 mum silicon membranes, achieving a loss related power density approaching 100 W/cm2 ). This paper reports on membrane power devices with current densities which approach the best of those offered by vertical devices (current density greater than 100 A/cm with power density of 180 W/cm2 ), without sacrificing switching speed (toff < 60 ns for 1.5 mum membranes). HTRB results showing 1000 h+ operation at 125degC at 80% of the rated voltage are also presented. Finally, it is shown that both the static and dynamic high temperature operation of thick membrane LIGBTs is superior to that of state-of-the-art integrated LDMOSFETs.

Buried field rings - a novel edge termination method for 4H-SiC high voltage devices

This paper is concerned with a numerical study of a novel edge breakdown termination technique for 4H-SiC high voltage devices. Buried field rings (BFRs) are proposed to be used, for the first time, in SiC devices as an effective termination method and the concept is numerically demonstrated for 4H-SiC MESA JFET structures. By using 4 BFRs for a MESA JFET, a breakdown voltage of 1,590 V has been achieved, representing more than 90% of the ideal bulk breakdown value (1,750 V). The influence of the buried rings doping on the blocking mode behaviour and the effect of the SiC/SiO/sub 2/ interface charge on the breakdown voltage are studied. It is evidenced that the BFR termination offers a very stable blocking mode behaviour and the influence of processing conditions on its over-all performance is negligible. For comparison, some results for guard rings and junction termination extension are also presented.

A numerical comparison between MOS control and junction control high voltage devices in SiC technology

Abstract A comprehensive numerical comparison between MOS control (MOSFETs) and junction control (JFETs) devices in SiC technology is presented. The study is carried out using the MEDICI device simulator and covers an interval of blocking voltages ranging from 600 V to 6.5 kV. The gate oxide failure phenomenon in SiC trench MOSFETs is studied and the effect of wide trenches and rounded trench corners on the voltage blocking performance is investigated. The paper continues with a comparative study of SiC MOSFETs and SiC JFETs. The JFET chosen has a particular channel geometry featuring a highly doped buffer layer to reduce the on-state resistance. The influence of the buffer layer and the gate voltage on the JFET on-state/breakdown performance is carefully investigated. The study concludes with a mixed-mode simulation of the transient behaviour of a 1.2 kV SiC JFET–Silicon MOSFET pair in a CASCODE configuration as a viable alternative to a single switch (either SiC MOSFET or JFET).

Towards fully integrated SiC cascade power switches for high voltage applications

This paper presents an advanced numerical analysis of novel hybrid silicon/SiC multiple cascode configuration. The novel approach is exemplified through a three device cascode Configuration, whereby a 5-20V silicon MOSFET blocks a lateral medium voltage 60-100V SiC JFET, which in turn reverse biases the gate of a vertical high voltage (/spl ges/1.2kV) SiC JFET. Furthermore, an elegant solution for the SiC part of the hybrid multiple cascode is also presented. A fully integrated SiC cascoded JFETs chip is proposed and numerically demonstrated. The results obtained through mixed mode simulations for the two cascode configurations are compared.

Point injection in trench insulated gate bipolar transistor for ultra low losses

In this paper we propose novel designs that enhance the plasma concentration across the Field Stop IGBT. The “p-ring” and the “point-injection” type devices exhibit increased cathode side conductivity modulation which results in impressive IGBT performance improvement. These designs are shown to be extremely effective in lowering the on-state losses without compromising the switching performance or the breakdown rating. For the same switching losses we can achieve more than 20% reduction of the on state energy losses compared to the conventional FS IGBT.

Analysis of static and dynamic behaviour of SiC and Si devices connected in cascode configuration

This paper presents an analysis of the static and dynamic behaviour of a 1.2 kV SiC vertical JFET. The JFET can block voltages up to 1450 V (for V/sub GS/=80 V), with a specific on-resistance as low as 2.3 m/spl Omega/cm/sup 2/. The mixed-mode performance is investigated by coupling the SiC JFET in a cascode circuit with a low power Si MOSFET. Comparing the circuit performance to that of a SiC trench MOSFET, it turns out that the SiC/Si cascode is almost twice faster than the MOSFET. Coupling this with the fact that the SiC/Si cascode pair has better on-state performance, it is concluded that the cascode is a superior alternative to the classical SiC trench MOSFET.

Evaluation of Termination Techniques for 4H-SiC Pin Diodes and Trench JFETs

An investigation concerning suitable termination techniques for 4H-SiC trench JFETs is presented. Field plates, p+ floating rings and junction termination extension techniques are used to terminate 1.2kV class PiN diodes. The fabricated PiN diodes evaluated here have a similar design to trench JFETs. Therefore, the conclusions for PiN diodes can be applied to JFET structures as well. Numerical simulations are also used to illustrate the effect of the terminations on the diodes’ blocking mode behaviour.

High performance SiC diodes based on an efficient planar termination

The paper addresses the state-of-art-in SiC power diodes. The best performance of Schottky barrier and junction barrier diodes on SiC is reviewed. The fundamental edge terminations used to relieve the crowding of the electric field of these devices are presented. An effective termination, based on the oxide ramp etching is described and the application of this method to SiC devices is discussed, achieving breakdown voltage of up to 95% from the ideally value.

A comprehensive analysis of breakdown mechanisms in 4H-SiC MOSFET and JFET

This paper presents a systematic analysis of breakdown mechanisms in silicon carbide MOSFET and JFET. For the MOSFET, the trench technology has been selected. The JFET structure is very similar to that having the distinctive feature of a buffer layer grown on the top of the drift region. Both devices are designed for 1.2 kV and were simulated and optimised using MEDICI and ISE TCAD software packages. This study indicates that the gate oxide breakdown puts a strong limitation on the electrical performance of the SiC trench MOSFET. Drawbacks encountered in SiC trench MOSFET, such as gate oxide breakdown, low channel mobility and the tight trade-off between the punch-through premature breakdown and the threshold voltage in the channel can be eliminated by using the SiC JFET.

High-voltage SiC devices: Diodes and MOSFETs

This paper reviews recent achievements on high-voltage SiC-based devices aimed at Wind Power and Solid-State Transformer applications. SiC diodes with voltage ranges between 1.7kV and 9kV have been designed and fabricated. On the other hand, SiC JFETs and, specially, SiC MOSFETs are also under development, and preliminary prototypes of 3.3 kV SiC MOSFETs are reported.