J. Millan

Buried field rings - a novel edge termination method for 4H-SiC high voltage devices

This paper is concerned with a numerical study of a novel edge breakdown termination technique for 4H-SiC high voltage devices. Buried field rings (BFRs) are proposed to be used, for the first time, in SiC devices as an effective termination method and the concept is numerically demonstrated for 4H-SiC MESA JFET structures. By using 4 BFRs for a MESA JFET, a breakdown voltage of 1,590 V has been achieved, representing more than 90% of the ideal bulk breakdown value (1,750 V). The influence of the buried rings doping on the blocking mode behaviour and the effect of the SiC/SiO/sub 2/ interface charge on the breakdown voltage are studied. It is evidenced that the BFR termination offers a very stable blocking mode behaviour and the influence of processing conditions on its over-all performance is negligible. For comparison, some results for guard rings and junction termination extension are also presented.

Design of Digital Electronics for High Temperature Using Basic Logic Gates Made of 4H-SiC MESFETs

– 4H-SiC MESFET transistors are very attractive devices for high temperature application and communications. The JFET and MESFET transistors have a promising potential for integrated circuits able to operate at high temperature and harsh radiation environments, due to the superior electrical, mechanical and chemical proprieties of 4H-SiC. Progresses in the manufacturing of high quality SiC substrates open the possibility to new circuit applications.

An IGBT gate driver integrated circuit with full-bridge output stage and short circuit protections

This paper presents a monolithic IGBT gate driver design with an original full-bridge topology output stage, implemented with high voltage LDMOSFETS (36-160V/1A) for power integrated circuits using standard low cost 2.5/spl square/m CMOS technology and oriented for digital applications. Short circuit protections have been also integrated. The full-bridge topology allows obtaining positive and negative gate voltages using a single floating power supply and the implementation of a soft shutdown process following a short circuit fault can be easily reached.

Gate Oxide Stability of 4H-SiC MOSFETs under On/Off-State Bias-Temperature Stress

On- and off-state bias-temperature instability (BTI) measurements of 4H-SiC field effect transistors fabricated in a gate-oxide-first process were performed in the 30-450 °C temperature range. Stable operation under off-state stress at 300 °C is reported. On-state bias-instability stress revealed behavior consistent with the presence of hole traps in the SiC channel. The interface state density Dit increased from 2.5 eV-1cm-2 to 6.6 eV-1cm-2 as a function of positive stress duration.

Complementary high voltage MOSFETs using a modified standard CMOS process

This paper presents a new high voltage technology for power integrated circuits using standard low cost 2.5 /spl mu/m CMOS technology and oriented for digital applications, with only one extra processing step. Lateral N- and P-MOSFET transistors have been optimized using 2D simulators attending both specific on-resistance and breakdown voltage. Lateral double diffused n-channel transistors with breakdown voltage of 160V (R/sub on/= 13.5m/spl Omega//spl middot/cm/sup 2/) have been achieved. Extended drain P-MOSFET transistors with low on-resistance and breakdown voltage of 36V (R/sub on/=2.0m/spl Omega//spl middot/cm/sup 2/) have been also implemented.

Electrical parameter variation of PT-IGBT by backside proton irradiation

This paper describes the lifetime killing processes performed on 600V PT-IGBTs in order to improve their switching behaviour. The devices were proton irradiated from the backside at different doses and ion penetration ranges. Static and dynamic characterization allowed determining the effect of both variables on forward voltage drop, turn-off time and leakage current. Optimal irradiation conditions have been identified to reach the best trade-off between these electrical parameters.

Novel techniques for reducing self-heating effects in silicon-on-insulator power devices

Self-heating effects in Silicon-On-Insulator (SOI) power devices have become a serious problem when the active silicon layer thickness is reduced and buried oxide thickness is increased. In order to alleviate the self-heating, two novel techniques which lead to a better heat flow from active silicon layer to silicon substrate through the buried oxide layer in SOI power devices are proposed. No significant changes on device electrical characteristics are expected with the inclusion of the novel techniques. The electro-thermal performance of lateral power devices including the proposed techniques is also presented.

MEDICI simulation of 6H-SiC oxide ramp profile (ORP) Schottky structure

A MEDICI simulation of 6H-SiC Schottky structure which uses the oxide ramp etching technique in order to attenuate edge effects is reported. The results of simulation show a uniform reverse current density and volume breakdown at Schottky structure with 300 V blocking voltage can be obtained for a maximum 5 degs, ramp angle of 1 /spl mu/m oxide.

High Voltage SiC Schottky Diodes in Rectifiers for X-Ray Generators

Silicon-Carbide-based semiconductors offer realization of efficient high voltage components, with high switching speed and low conduction losses. SiC Schottky diodes with safe blocking capability of at least 4 kV were produced and characterized. A simulation model for loss determination was developed. Real losses were determined on a small scale test setup and chip temperature distribution was obtained from that, combined with FEM calculation. A full-size rectifier 100 kW/140 kV-SiC-rectifier module with six times higher power density than with conventional Si-technology was realized.

Integration of Temperature and Current Sensors in 4H-SiC VDMOS

Silicon Carbide VDMOS with integrated current and temperature sensors have been successfully fabricated without degradation of the chip forward or reverse characteristics due to the sensors. The temperature sensors show impedance correlated to the temperature, which permits to track the drift region’s temperature of the device. We have shown that the sensor current ratio can be influenced by the current spreading in the drift layer, especially when the channel resistance contribution is reduced. This aspect will be more critical on VDMOS with low channel resistance. Also, the sensor current ratio stability will be improved on devices with larger active area or thinner drift layer. Integration of such sensors will permit to monitor and protect innovative power electronic systems using SiC chips.