A. N. Nagamani

Progress in Reversible Processor Design: A Novel Methodology for Reversible Carry Look-Ahead Adder

Reversible logic is playing a significant role in quantum computing as quantum operations are unitary in nature. Quantum computer performs computation at an atomic level; thereby doing high performance computations beyond the limits of the conventional computing systems. Reversible arithmetic units such as adders, subtractors, multipliers form the essential component of a quantum computing system. Among the adder designs, carry look-ahead is widely used in high performance computing due to its O (log n) depth. In this work, we present improved designs of both in-place and out-of-place reversible carry look-ahead adder proposed in [1]. The proposed designs utilize the properties of the reversible Peres gate and the TR gate to optimize the logic depth, quantum cost and gate count compared to the existing designs proposed in [1]. Both the improved designs assume no input carry (C0=0). While the first approach makes use of ancilla bits to store the sum outputs, the second approach stores the sum outputs in one of the input locations.

Efficient design and FPGA implementation of JPEG encoder using verilog HDL

The JPEG encoder is a major component in JPEG standard which is used in image compression. It involves a complex sub-block discrete cosine transform (DCT), along with other quantization, zigzag and Entropy coding blocks. In this paper verilog design and hardware implementation of pipelined 2-D DCT along with zigzag, quantization and variable length coding is described. 2-D DCT is computed by combining two 1-D DCT that connected by a transpose buffer. The architecture uses 4059 slices 6885 LUT, 58 I/Os of Xilinx Spartan-3 XC3S1500 FPGA and works at an operating frequency of 65.55 MHz. The delay of processing each 8*8 block in an image is also evaluated to be 1.47micro seconds.

Design of optimized reversible binary adder/subtractor and BCD adder

Reversible logic has gained the interest of many researchers due to its applicability in emerging low power technologies such as Quantum computing, QCA, optical computing etc., Adders/Subtractors are basic design components of any processor. Optimized design of these adders results in efficient processors. In this work we propose optimized Binary adders/subtractors and BCD adders. The adders/subtractors designed in this work are optimized for Quantum cost and Delay. We also propose a generic design of n-bit adders and subtractors. In this work, we explore the use of Negative control lines for detecting overflow logic of BCD adder which considerably reduces Quantum cost, delay and gate count which result in high speed BCD adder with optimized area which give way to lot of scope in the field of reversible computing in near future.

An Exact approach for Complete Test Set Generation of Toffoli-Fredkin-Peres based Reversible Circuits

Reversible logic has gained interest of researchers worldwide for its ultra-low power and high speed computing abilities in the future quantum information processing. Testing of these circuits is important for ensuring high reliability of their operation. In this work, we propose an ATPG algorithm for reversible circuits using an exact approach to generate CTS (Complete Test Set) which can detect single stuck-at faults, multiple stuck-at faults, repeated gate fault, partial and complete missing gate faults which are very useful logical fault models for reversible logic to model any physical defect. Proposed algorithm can be used to test a reversible circuit designed with k-CNOT, Peres and Fredkin gates. Through extensive experiments, we have validated our proposed algorithm for several benchmark circuits and other circuits with family of reversible gates. This algorithm produces a minimal and complete test set while reducing test generation time as compared to existing state-of-the-art algorithms. A testing tool is developed satisfying the purpose of generating all possible CTS’s indicating the simulation time, number of levels and gates in the circuit. This paper also contributes to the detection and removal of redundant faults for optimal test set generation.

Reversible Radix-4 booth multiplier for DSP applications

Power dissipation has become the major concern for circuit design and implementation. Reversible Logic is the best alternative to Irreversible Logic in terms of low power consumption. Circuits designed using reversible logic have a wide array of applications. The Quantum Cost, Garbage Outputs, Ancillary Inputs and Delay are some of the parameters of reversible circuits that can be used to determine their efficiency and compare them with existing works. Optimization of these parameters are highly essential. Garbage Outputs is an important parameter that must be considered. This paper presents a design for a Reversible Radix-4 Booth Multiplier that is optimized in Garbage Cost and Ancillary inputs. The design proposed is capable of both signed and unsigned multiplication. The optimization in Garbage Cost ensures lower heat dissipation. The Encoded Booth Algorithm or Radix-4 Booth Algorithm reduces the number of partial products generated in signed multiplication to half the number generated using a Radix-2 signed multiplier making it suitable for Digital Signal Processors. The design proposed is compared to existing multiplier circuits and the parameters are tabulated.

Design and Analysis of Reversible Binary and BCD Adders

Reversible logic in recent times has attracted a lot of research attention in the field of Quantum computation and nanotechnology due to its low power dissipation capability. Adders are one of the basic components in most of digital systems. Optimization of these adders can improve the performance of the entire system. In this work we have proposed designs of reversible Binary and BCD adders. Ripple carry adder, conditional adders for binary addition and regular and flagged adders for BCD addition. The proposed adder designs are optimized for quantum cost, Gate count and delay. The effectiveness of the negative control Toffoli and Peres gates in reducing quantum cost, delay and gate count is explored. Due to this the adder performance increases along with area optimization which will make these designs useful in future low power Reversible computing.

Design and performance evaluation of Hybrid Prefix Adder and carry increment adder in 90nm regime

This paper presents an implementation of two 8-bit adders (HPA and CIA) and comparing their performance with respect to power delay product for different voltages in 90 nm regime. HPA is derived from Parallel prefix adders for minimized Power Delay product. CIA is derived from carry select adder with reduced area scheme for carry-select adders lowers this overhead by computing the carry and sum bits for a block-carry-in value of 0 only and by incrementing them afterwards depending on the final block-carry- in. For 8-bit implementation of carry generation, HPA needs 158 transistors where as CIA needs 282 transistors. HPA gives reduced power delay product compared to CIA. Tanner EDA tool is used for schematic implementation and simulating the adder designs in the 90nm technology

A Genetic Algorithm-Based Heuristic Method for Test Set Generation in Reversible Circuits

Low power circuit design has been one of the major growing concerns in integrated circuit technology. Reversible circuit (RC) design is a promising future domain in computing which provides the benefit of less computational power. With the increase in the number of gates and input variables, the circuits become complex and the need for fault testing becomes crucial in ensuring high reliability of their operation. Various fault detection methods based on exhaustive test vector search approaches have been proposed in the literature. With increase in circuit complexity, a faster test generation method for providing optimal coverage becomes desirable. In this paper, a genetic algorithm-based heuristic test set generation method for fault detection in RCs is proposed which avoids the need for an exhaustive search. Two approaches, one involving random search and the other, involving directed search have been proposed and validated on benchmark circuits considering missing-gate fault (complete and partial), bridging fault and stuck-at fault with optimum coverage and reduced computational efforts.

Design of register file using reversible logic

Register file is the paramount aspect in computer memory unit. Eight bits (one memory unit) results in a single register and 32 of such register make up a register file. In this paper w e have presented the design of a complete register file using reversible logic design. It consists of decoder, multiplexer, memory unit, read and write units. This has been verified using VHDL. In addition to that, we have implemented the register file in the design of Content Addressable Memory (CAM) as an application.

Design and Analysis of Multiple Parameters Optimized n-Bit Reversible Magnitude Comparators

Reversible logic has gained its importance in the field of low power digital design. In any digital system, the comparator plays an important role in determining whether the two referenced numbers are either equal, greater or lesser. This work deals with optimization of existing reversible comparator designs and also proposes a new multiplexer-based logic for the design of reversible comparator along with design methodology for n-bit comparators. The proposed design is optimized for multiple performance parameters compared to the existing state-of-the-art designs. The proposed multiplexer-based design has 51.9% improvement in quantum cost, 50% in garbage outputs and 62% in ancilla inputs. These optimized designs find application predominantly in the field of quantum computing for low power signal processing, parallel computing, memories, digital system design and multi-processing.