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Dive into the research topics where A. P. Vinod is active.

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Featured researches published by A. P. Vinod.


IEEE Transactions on Biomedical Engineering | 2009

A New Discriminative Common Spatial Pattern Method for Motor Imagery Brain–Computer Interfaces

Kavitha P. Thomas; Cuntai Guan; Chiew Tong Lau; A. P. Vinod; Kai Keng Ang

Event-related desynchronization/synchronization patterns during right/left motor imagery (MI) are effective features for an electroencephalogram-based brain-computer interface (BCI). As MI tasks are subject-specific, selection of subject-specific discriminative frequency components play a vital role in distinguishing these patterns. This paper proposes a new discriminative filter bank (FB) common spatial pattern algorithm to extract subject-specific FB for MI classification. The proposed method enhances the classification accuracy in BCI competition III dataset IVa and competition IV dataset IIb. Compared to the performance offered by the existing FB-based method, the proposed algorithm offers error rate reductions of 17.42% and 8.9% for BCI competition datasets III and IV, respectively.


international symposium on circuits and systems | 2008

Coefficient decimation approach for realizing reconfigurable finite impulse response filters

R. Mahesh; A. P. Vinod

A new approach to implement computationally efficient reconfigurable finite impulse response (FIR) filter is presented in this paper. If the coefficients of an FIR filter are decimated by M, i.e., if every Mth coefficient of the filter is kept unchanged and remaining coefficients are changed to zeros, a multi-band frequency response will be obtained. The resulting frequency responses will have centre frequencies at 2pik/M, where k is an integer ranging from 0 to M-1. If these multi-band frequency responses are selectively masked using inherently low complex wide transition-band masking filters, different low-pass, high-pass, bandpass, and bandstop filters can be obtained. If every Mth coefficient is grouped together removing the zero coefficients in between, a decimated frequency response in comparison to the original frequency response is obtained. In this paper, we also show the design of a reconfigurable filter bank using the above approach.


international symposium on circuits and systems | 2007

Design of Reversible Sequential Elements With Feasibility of Transistor Implementation

Himanshu Thapliyal; A. P. Vinod

This paper presents the novel designs of reversible sequential circuits (latches and flip flops). The proposed reversible latches and flip flops are designed from reversible Fredkin, Feynman and Toffoli gates. Two new reversible gates called modified Fredkin gate (MFG) and modified Toffoli gate (MTG) are also proposed to design the optimized implementations. The proposed designs are better than the recently proposed ones in terms of number of reversible gates and garbage outputs. In order to reach towards the goal of transistor implementations of proposed reversible sequential circuits, transistor implementation of the existing Feynman gate, Fredkin gate, Toffoli gates as well as the proposed MTG and MFG are also proposed. The proposed transistor implementations are completely reversible in nature, i.e., suitable for both the forward and backward computation.


IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2005

On the implementation of efficient channel filters for wideband receivers by optimizing common subexpression elimination methods

A. P. Vinod; E.M.-K. Lai

The most computationally intensive part of a wideband receiver is the channelizer. The computational complexity of linear phase finite impulse response (LPFIR) filters employed in the channelizer is dominated by the number of adders used in the implementation of the multipliers. In this paper, two methods are proposed to efficiently implement the channel filters in a wideband receiver based on common subexpression elimination (CSE). We exploit the fact that a significant amount of redundant multiplications exist in the filter-bank channelizer as it extracts multiple narrowband channels from the wideband signal. By forming three and four nonzero-bit super-subexpressions utilizing redundant identical shifts that exist between a two- nonzero-bit common subexpression (CS) and a third nonzero bit, or between two nonzero-bit CS, the number of adders to implement the channel filters can be reduced considerably. Furthermore, the complexity of the adders is analyzed and design examples of the channel filters employed in the digital advanced mobile phone system (D-AMPS) and the personal digital cellular (PDC) channelizers show that the proposed methods offer considerable reduction in the number of full adders when compared to conventional CSE methods.


IEEE Transactions on Circuits and Systems | 2008

Information Theoretic Approach to Complexity Reduction of FIR Filter Design

Chip-Hong Chang; Jiajia Chen; A. P. Vinod

This paper presents a new paradigm of design methodology to reduce the complexity of application-specific finite-impulse response (FIR) digital filters. A new adder graph data structure called the multiroot binary partition graph (MBPG) is proposed for the formulation of the multiple constant multiplication problem of FIR filter design. The set of coefficients in any fixed point representation is partitioned into symbols so that common subexpression identification and elimination become congruent to information parsing for data compression. A minimum number of different pairs or groups of symbols and residues can be used to code a set of coefficients based on their probability and conditional probability of occurrence. This ingenious concept enables the notion of entropy to be applied as a quantitative measure to evaluate the coding density of different compositions of symbols towards a set of coefficients. The minimal vertex set MBPG synthesized by our proposed information theoretic approach results in direct correspondences between the vertices and adders, and edges and physical interconnections. Unlike the common subexpression elimination algorithms based on other graph data structures, the symbol-level information carried in each vertex and the graph isomorphism of MBPG promise further fine-grain optimization in a reduced search space. One such optimization that has been exploited in this paper is the shift-inclusive computation reordering to minimize the width of every twos complement adder to further reduce the implementation cost and the critical path delay of the filter. Experiment results show that the proposed algorithm can contribute up to 19.30% reductions in logic complexity and up to 61.03% reduction in critical path delay over other minimization methods.


IEEE Transactions on Wireless Communications | 2006

Low power and high-speed implementation of fir filters for software defined radio receivers

A. P. Vinod; Edmund Ming-Kit Lai

The most computationally intensive part of the wideband receiver of a software defined radio (SDR) is the intermediate frequency (IF) processing block. Digital filtering is the main task in IF processing. The computational complexity of finite impulse response (FIR) filters used in the IF processing block is dominated by the number of adders (subtracters) employed in the multipliers. This paper presents a method to implement FIR filters for SDR receivers using minimum number of adders. We use an arithmetic scheme, known as pseudo floating-point (PFP) representation to encode the filter coefficients. By employing a span reduction technique, we show that the filter coefficients can be coded using considerably fewer bits than conventional 24-bit and 16-bit fixed-point filters. Simulation results show that the magnitude responses of the filters coded in PFP meet the attenuation requirements of wireless communication standard specifications. The proposed method offers average reductions of 40% in the number of adders and 80% in the number of full adders needed for the coefficient multipliers over conventional FIR filter implementation methods


Journal of Neural Engineering | 2013

Multi-class EEG classification of voluntary hand movement directions.

Neethu Robinson; Cuntai Guan; A. P. Vinod; Kai Keng Ang; Keng Peng Tee

OBJECTIVE Studies have shown that low frequency components of brain recordings provide information on voluntary hand movement directions. However, non-invasive techniques face more challenges compared to invasive techniques. APPROACH This study presents a novel signal processing technique to extract features from non-invasive electroencephalography (EEG) recordings for classifying voluntary hand movement directions. The proposed technique comprises the regularized wavelet-common spatial pattern algorithm to extract the features, mutual information-based feature selection, and multi-class classification using the Fisher linear discriminant. EEG data from seven healthy human subjects were collected while they performed voluntary right hand center-out movement in four orthogonal directions. In this study, the movement direction dependent signal-to-noise ratio is used as a parameter to denote the effectiveness of each temporal frequency bin in the classification of movement directions. MAIN RESULTS Significant (p < 0.005) movement direction dependent modulation in the EEG data was identified largely towards the end of movement at low frequencies (≤6 Hz) from the midline parietal and contralateral motor areas. Experimental results on single trial classification of the EEG data collected yielded an average accuracy of (80.24 ± 9.41)% in discriminating the four different directions using the proposed technique on features extracted from low frequency components. SIGNIFICANCE The proposed feature extraction strategy provides very high multi-class classification accuracies, and the results are proven to be more statistically significant than existing methods. The results obtained suggest the possibility of multi-directional movement classification from single-trial EEG recordings using the proposed technique in low frequency components.


IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2005

An efficient coefficient-partitioning algorithm for realizing low-complexity digital filters

A. P. Vinod; E.M.-K. Lai

Algorithms that minimize the complexity of multiplication in digital filters focus on reducing the number of adders needed to implement the coefficient multipliers. Previous works have not analyzed the complexity of each adder, which is significant in low-complexity implementation. A multiplication algorithm for low-complexity implementation of digital filters with a minimum number of full adders (NFAs) and improved speed is proposed here. The authors exploit the fact that when multiplication is implemented using shifts and adds, the adder width can be minimized by limiting the shifts of the operands to shorter lengths. The coefficient-partitioning (CP) algorithm proposed here minimizes the shifts of the operands of the adders by partitioning each coefficient into two subcomponents. The authors show that by combining three methods, the CP algorithm, an efficient coefficient coding scheme known as pseudo floating-point (PFP) representation, and the well-known common subexpression elimination (CSE), the NFAs required in each adder of the multiplier can be reduced considerably. Design examples show that the method offers an average FA reduction of 30% for finite-impulse response (FIR) filters and 20% for infinite-impulse response (IIR) filters over CSE methods.


personal, indoor and mobile radio communications | 2003

A reconfigurable multi-standard channelizer using QMF trees for software radio receivers

A. P. Vinod; E.M.-K. Lai; A. B. Premkumar; Chiew-Tong Lau

The flexibility of a software-defined radio (SRR) depends on its capability to operate in multi-standard wireless communication environments. The most computationally intensive part of wideband receivers is the channelizer, which extracts multiple narrowband signals from adjacent frequency hands. In an SDR receiver, the compatibility of the channelizer with different communication standards is guaranteed by its reconfigurability. This paper presents an efficient channelizer that has a reconfigurable architecture based on quadrature mirror filter bank (QMF) trees. We show that the channelizer can he efficiently implemented using common subexpression based filter structures. An example of dual-mode global system for mobile communication (GSM)/personal digital cellular (PDC) channelizer is discussed to illustrate the proposed design methodology.


international conference of the ieee engineering in medicine and biology society | 2013

Design of an online EEG based neurofeedback game for enhancing attention and memory

Kavitha P. Thomas; A. P. Vinod; Cuntai Guan

Brain-Computer Interface (BCI) is an alternative communication and control channel between brain and computer which finds applications in neuroprosthetics, brain wave controlled computer games etc. This paper proposes an Electroencephalogram (EEG) based neurofeedback computer game that allows the player to control the game with the help of attention based brain signals. The proposed game protocol requires the player to memorize a set of numbers in a matrix, and to correctly fill the matrix using his attention. The attention level of the player is quantified using sample entropy features of EEG. The statistically significant performance improvement of five healthy subjects after playing a number of game sessions demonstrates the effectiveness of the proposed game in enhancing their concentration and memory skills.

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K. G. Smitha

Nanyang Technological University

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Kavitha P. Thomas

Nanyang Technological University

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Cuntai Guan

Nanyang Technological University

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Abhishek Ambede

Nanyang Technological University

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R. Mahesh

Nanyang Technological University

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A. S. Madhukumar

Nanyang Technological University

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Neethu Robinson

Nanyang Technological University

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Edmund M-K. Lai

Auckland University of Technology

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