R. Mahesh

New Reconfigurable Architectures for Implementing FIR Filters With Low Complexity

Reconfigurability and low complexity are the two key requirements of finite impulse response (FIR) filters employed in multistandard wireless communication systems. In this paper, two new reconfigurable architectures of low complexity FIR filters are proposed, namely constant shifts method and programmable shifts method. The proposed FIR filter architecture is capable of operating for different wordlength filter coefficients without any overhead in the hardware circuitry. We show that dynamically reconfigurable filters can be efficiently implemented by using common subexpression elimination algorithms. The proposed architectures have been implemented and tested on Virtex 2v3000ff1152-4 field-programmable gate array and synthesized on 0.18 ¿m complementary metal-oxide-semiconductor technology with a precision of 16 bits. Design examples show that the proposed architectures offer good area and power reductions and speed improvement compared to the best existing reconfigurable FIR filter implementations in the literature.

A New Common Subexpression Elimination Algorithm for Realizing Low-Complexity Higher Order Digital Filters

The complexity of linear-phase finite-impulse-response (FIR) filters is dominated by the complexity of coefficient multipliers. The number of adders (subtractors) used to implement the multipliers determines the complexity of the FIR filters. It is well known that common subexpression elimination (CSE) methods based on canonical signed digit (CSD) coefficients reduce the number of adders required in the multipliers of FIR filters. A new CSE algorithm using binary representation of coefficients for the implementation of higher order FIR filters with a fewer number of adders than CSD-based CSE methods is presented in this paper. We show that the CSE method is more efficient in reducing the number of adders needed to realize the multipliers when the filter coefficients are represented in the binary form. Our observation is that the number of unpaired bits (bits that do not form CSs) is considerably few for binary coefficients compared to CSD coefficients, particularly for higher order FIR filters. As a result, the proposed binary-coefficient-based CSE method offers good reduction in the number of adders in realizing higher order filters. The reduction of adders is achieved without much increase in critical path length of filter coefficient multipliers. Design examples of FIR filters show that our method offers an average adder reduction of 18% over the best known CSE method, without any increase in the logic depth.

Reconfigurable Frequency Response Masking Filters for Software Radio Channelization

Low complexity and reconfigurability are two key requirements of channel filters in a software defined radio receiver. A new reconfigurable architecture based on frequency response masking (FRM) technique for the implementation of channel filters is proposed in this paper. Our architecture offers reconfigurability at filter and architecture levels, in addition to the inherent low complexity offered by the FRM technique. The proposed reconfigurable filter has been synthesized on 0.18- CMOS technology and implemented and tested on Virtex-II 2v3000ff1152-4 field-programmable gate array. Synthesis results show that the proposed channel filter offers average area and power reductions of 53.6% and 57.6%, respectively ,with average improvement in speed of 47.6% compared to other reconfigurable filters in literature.

Filter Bank Channelizers for Multi-Standard Software Defined Radio Receivers

The ability to support multiple channels of different communication standards, in the available bandwidth, is of importance in modern software defined radio (SDR) receivers. An SDR receiver typically employs a channelizer to extract multiple narrowband channels from the received wideband signal using digital filter banks. Since the filter bank channelizer is placed immediately after the analog-to-digital converter (ADC), it must operate at the highest sampling rate in the digital front-end of the receiver. Therefore, computationally efficient low complexity architectures are required for the implementation of the channelizer. The compatibility of the filter bank with different communication standards requires dynamic reconfigurability. The design and realization of dynamically reconfigurable, low complexity filter banks for SDR receivers is a challenging task. This paper reviews some of the existing digital filter bank designs and investigates the potential of these filter banks for channelization in multi-standard SDR receivers. We also review two low complexity, reconfigurable filter bank architectures for SDR channelizers based respectively on the frequency response masking technique and a novel coefficient decimation technique, proposed by us recently. These filter bank architectures outperform existing ones in terms of both dynamic reconfigurability and complexity.

Low complexity flexible filter banks for uniform and non-uniform channelisation in software radios using coefficient decimation

A new approach to implement computationally efficient reconfigurable filter banks (FBs) is presented. If the coefficients of a finite impulse response filter are decimated by M, that is, if every Mth coefficient of the filter is kept unchanged and remaining coefficients are replaced by zeros, a multi-band frequency response will be obtained. The frequency response of the decimated filter will have bands with centre frequencies at 2πk/M, where k is an integer ranging from 0 to M−1. If these multi-band frequency responses are subtracted from each other or selectively masked using inherently low complex wide transition-band masking filters, different low-pass, high-pass, band-pass and band-stop frequency bands are obtained. The resulting FB, whose bands’ centre frequencies are located at integer multiples of 2π/M, is a low complexity alternative to the well-known uniform discrete Fourier transform FBs (DFTFBs). It is shown that the channeliser based on the proposed FB does not require any DFT for its implementation unlike a DFTFB. It is also shown that the proposed FB is more flexible and easily reconfigurable than the DFTFB. Furthermore, the proposed FB is able to receive channels of multiple standards simultaneously, whereas separate FBs would be required for simultaneous reception of multi-standard channels in a DFTFB-based receiver. This is achieved through a second stage of coefficient decimation. Implementation result shows that the proposed FB offers an area reduction of 41% and improvement in the speed of 50.8% over DFTFBs.

Reconfigurable Low Area Complexity Filter Bank Architecture Based on Frequency Response Masking for Nonuniform Channelization in Software Radio Receivers

The most computationally demanding block in the digital front-end of a software defined radio (SDR) receiver is the channelizer which operates at the highest sampling rate. Channelizers are employed in the SDR receivers for extracting individual channels (frequency bands) from the digitized wideband input signal. Reconfigurability and low complexity are the two key requirements in an SDR channelizer. A new reconfigurable filter bank (FB) architecture based on frequency response masking (FRM) for SDR channelizers is proposed. The proposed FB offers reconfigurability at the architectural level and at the channel filter level and is capable of extracting channels of nonuniform bandwidths corresponding to multiple wireless communication standards from the digitized wideband input signal. Design examples show that the proposed FB offers multiplier complexity reduction of 84% over the conventional per-channel (PC) approach, which is best suitable for the extraction of channels of nonuniform bandwidth. The proposed FB has been synthesized on 0.18 μm complementary metal oxide semiconductor (CMOS) technology and compared with the PC approach. Synthesis results show that the proposed FB offers area reduction of 85%, power reduction of 48.5%, and improvement in speed of 56.7% over the PC approach. The proposed FB has been implemented on Xilinx Virtex 2v3000ff1152-4 FPGA and tested using real-time inputs from a vector signal generator.

A Low-Complexity Flexible Spectrum-Sensing Scheme for Mobile Cognitive Radio Terminals

Low-complexity and flexible spectrum sensing is one of the challenging tasks in a cognitive radio (CR). Most of the work on energy-detection-based spectrum sensing presented in the literature employ a filter bank (FB) to split the wideband input signal into several subbands and detect the spectrum by computing the energy of subbands. However, for a mobile CR handset, a filter-bank-based spectrum sensing is not an area- and power-efficient scheme. In this paper, a novel spectrum-sensing scheme based on a reconfigurable digital downconverter (RDDC) and a reconfigurable filter based on coefficient decimation is proposed for mobile CR handsets, which has very low complexity and high flexibility compared to conventional FB approaches. The basic idea is to rotate the spectrum using an RDDC and filter the desired portion of the spectrum using the reconfigurable filter, which then results in very low complexity. The implementation results on Virtex-4 field-programmable gate array show that our method offers significant reductions in gate count, power consumption, and delay over conventional discrete Fourier transform FB-based spectrum sensing.

Reconfigurable discrete Fourier transform filter banks for multi-standard channelizers

In a wireless communication receiver, channelization is the process of extracting individual narrowband radio channels from the digitized wideband input signal and providing these channels at baseband for further processing. Discrete Fourier transform filter banks (DFTFBs) are widely employed for the channelization purpose. This is because they efficiently utilize the polyphase decomposition of the prototype filter so that the prototype filter can be operated at a significantly reduced sampling rate. However DFTFBs suffer from the drawback that they can be employed only for the extraction of channels of uniform bandwidths. In this paper, a new DFTFB is presented which can be reconfigured with minimal overhead to extract channels of different bandwidths. The proposed DFTFB consists of a prototype filter which employs the concept of coefficient decimation for obtaining different passband widths. From the analysis of the architecture, it is clear that the overhead in the proposed filter bank is only few extra adders when compared to the conventional uniform DFTFB. Implementations results show that the proposed filter bank offers area and power reductions of 54% and 42% and speed improvement of 30.5% over conventional DFTFB respectively.

A new low complexity reconfigurable filter bank architecture for software radio receivers based on interpolation and masking technique

The most computationally demanding block in the digital front end (DFE) of a software defined radio (SDR) is the channelizer which operates at the highest sampling rate. Channelizers are employed in the SDR receivers for extracting individual channels from the digitized wideband input signal. Reconfigurability and low complexity are the two key requirements of channelizers in SDRs. A new reconfigurable filter bank (FB) architecture based on an interpolation and masking technique for SDR channelizers is proposed in this paper. The proposed FB offers reconfigurability at the architectural level and at the channel filter level, and is capable of extracting channels of different bandwidths corresponding to multiple wireless communication standards from the digitized wideband input signal. Design example shows that the proposed FB offers complexity reduction of 89.9% over the conventional per-channel (PC) approach, 79.8% over DFT filter banks (DFTFBs).

An Area-efficient Non-uniform Filter Bank for Low Overhead Reconfiguration of Multi-standard Software Radio Channelizers

The channelizer in a software defined radio (SDR) base station extracts individual radio channels from the digitized wideband input signal at a very high sampling rate. The base station channelizer must be able to simultaneously extract multiple channels of non-uniform bandwidths corresponding to channel bandwidths of different communication standards. Reconfigurability and low complexity are the two key requirements in the SDR channelizer. A new reconfigurable filter bank (FB) architecture based on interpolation and masking technique for SDR channelizers is proposed in this paper. The proposed FB can be used for obtaining very narrow passband channels with extremely low complexity. Using a cascaded structure of the proposed FB, it is possible to extract channels of fractional passband widths by changing the interpolation factor. Design example shows that the proposed FB offers complexity reduction of 84% over the conventional per-channel (PC) approach. The proposed FB has been implemented and tested on Xilinx Virtex 2v3000ff1152-4 FPGA. Implementation results show that the proposed FB offers area reduction of 48.37%, speed improvement of 52.7% and power reduction of 75.9% over the PC approach.