A-Ram Choi

The low-frequency noise characteristics of p-type metal-oxide-semiconductor field effect transistors with a strained-Si0.88Ge0.12 channel grown on bulk Si and a PD-SOI substrate

Low-frequency noise properties have been investigated for SiGe p-type metal-oxide- semiconductor field effect transistors with different substrates using Si bulk and a partially depleted silicon-on-insulator (PD SOI). The electrical properties of SiGe PD SOI were enhanced in the subthreshold slope and drain induced barrier lowering. However, the low-frequency noise for the PD SOI was found to degrade significantly in terms of the power spectral density. The low frequency noise was observed to follow the typical 1/fγ(γ = 1) dependence in SiGe bulk devices, but abnormal changes with γ = 2 were revealed in the SiGe PD SOI. The difference of the noise frequency exponent was mainly attributed to generation–recombination by traps presented at the silicon–oxide interface of the SOI. Regardless of the degraded noise performance in the SOI structure, the low-frequency noise level remained well at an acceptable level by virtue of the effective carrier confinement in the SiGe channel.

Stress Effect Analysis for PD SOI pMOSFETs with Undoped-Si0.88Ge0.12 Heterostructure Channel

The stress effect of SiGe p-type metal oxide semiconductor field effect transistors (MOSFETs) has been investigated to compare their properties associated with the Si0.88Ge0.12/Si epi channels grown on the Si bulk and partially depleted silicon on insulator (PD SOI) substrates. The stress-induced changes in the subthreshold slope and the drain induced barrier lowering were observed small in the SiGe PD SOI in comparison to in the SiGe bulk. Likewise the threshold voltage shift monitored as a function of hot carrier stress time presented excellent stability than in the SiGe PD SOI. Therefore, simply in terms of do properties, the SiGe PD SOI looks more immune from electrical stresses than the SiGe bulk. However, the 1/f noise properties revealed that the hot carrier stress could introduce lots of generation-recombination noise sources in the SiGe PD SOI. The quality control of oxide-silicon in SOI structures is essential to minimize a possible surge of 1/f noise level due to the hot carrier injection. In order to improve dc and rf performance simultaneously, it is very important to grow the SiGe channels on high quality SOI substrates.

Selective Epitaxial Growth of SiGe Layers with High Aspect Ratio Mask of Dielectric Films

This paper presents the selective epitaxial growth (SEG) properties of reduced pressure chemical vapor deposition (RPCVD) at low temperatures (LT) of 675-725°C with high aspect ratio mask of dielectric films. The SEG process could be explained in conjunction with the loading effect, the mask pattern shape/size, and the process parameters of RPCVD. The growth rates showed a large non-uniformity up to 40% depending upon the pattern size of the dielectric mask films, but as the SEG film becomes thicker, the growth rate difference converged on -15% between the narrow 2-μm and the wide 100-μm patterns. The evolution of SEG was controlled dominantly by the surface migration control at the initial stage, and converted to the surface topology control. The design of pattern size and distribution with dummy patterns must be useful to accomplish the reliable and uniform LT-SEG.

Electrical Properties of SiGe HBTs designed with Bottom Collector and Single Metal Layer Structures

This paper presents the electrical properties of SiGe HBTs designed with bottom collector and single metal layer structure for RF power amplifier. Base layer was formed with graded-SiGe/Si structures and the collector place to the bottom of the device. Bottom collector and single metal layer structures could significantly simplify the fabrication process. We studied about the influence of SiGe base thickness, number of emitter fingers and temperature dependence

Comparison of Electrical Characteristics of SiGe pMOSFETs Formed on Bulk-Si and PD-SOI

( frequency from measured data using packaged SiGe HBTs. We will discuss the temperature dependent current flow through the e-b, b-c junctions to understand stability and performance of the device.

Low temperature selective epitaxial growth of SiGe layers using various dielectric mask patterns and process conditions

This paper has demonstrated the electrical properties of SiGe pMOSFETs fabricated on both bulk-Si and PD SOI substrates. Two principal merits, the mobility increase in strained-SiGe channel and the parasitic capacitance reduction of SOI isolation, resulted in improvements in device performance. It was observed that the SiGe PD SOI could alleviate the floating body effect, and consequently DIBL was as low as 10 mV/V. The cut-off frequency of device fabricated on PD SOI substrate was roughly doubled in comparison with SiGe bulk: from 6.7 GHz to 11.3 GHz. These experimental result suggests that the SiGe PD SOI pMOSFET is a promising option to drive CMOS to enhance performance with its increased operation frequency for high speed and low noise applications.