A. Ritenour

Ge diffusion in Ge metal oxide semiconductor with chemical vapor deposition HfO2 dielectric

We report a study on Ge diffusion and its impact on the electrical properties of TaN∕HfO2∕Ge metal-oxide-semiconductor (MOS) device. It is found that Ge diffusion depends on the amount of GeO2 formed at the HfO2∕Ge interface and can be retarded by surface nitridation. It is speculated that Ge diffusion is in the form of GeO or Ge-riched HfGeO. Effective suppression of Ge diffusion by NH3 nitridation has resulted in improved electrical properties of TaN∕HfO2∕Ge MOS device, including equivalent oxide thickness (EOT), leakage current, hysteresis, and interface state density. The degradation of leakage current after high temperature post metallization anneal (PMA) is found to be due to Ge diffusion.

Epitaxial strained germanium p-MOSFETs with HfO/sub 2/ gate dielectric and TaN gate electrode

Germanium p-MOSFETs with a thin high-k dielectric (EOT/spl sim/1.6 nm) were fabricated on bulk Ge and epitaxial germanium-on-silicon substrates. These devices exhibited sub-90 mV/decade subthreshold swing and low gate leakage. The IV and CV characteristics achieved in this work allow for accurate extraction of important device parameters such as transconductance (Gm) and low-field mobility. Results from n-MOSFETs fabricated on bulk Ge substrates are also presented.

Ge MOS characteristics with CVD HfO/sub 2/ gate dielectrics and TaN gate electrode

In this paper, we report for the first time Ge MOS characteristics with ultra thin rapid thermal CVD HfO/sub 2/ gate dielectrics and TaN gate electrode. Using the newly developed pre-gate cleaning and NH/sub 3/-based Ge surface passivation, the TaN/HfO/sub 2//Ge gate stack with EOT of 12.9 /spl Aring/ exhibits excellent leakage current density of 6 mA/cm/sup 2/ @Vg=1V and interface state density (D/sub it/) of 8/spl times/10/sup 10//cm/sup 2/-eV. Both D/sub it/ and CV hysteresis of Ge MOS are improved significantly with NH/sub 3/ surface treatment. We also study the effects of post-deposition anneal and investigate the conduction mechanism of TaN/HfO/sub 2//Ge gate stack.

Subnanometer-equivalent-oxide-thickness germanium p-metal-oxide-semiconductor field effect transistors fabricated using molecular-beam-deposited high-k/metal gate stack

Metal-oxide-semiconductor field effect transistors (MOSFET) with a thin high-k dielectric were fabricated on bulk n-type germanium substrates. Surface oxides were thermally desorbed in situ by heating the substrates under ultrahigh vacuum conditions. First an ultrathin passivating layer was formed by evaporating germanium in the presence of atomic oxygen and nitrogen supplied from a remote radio frequency plasma source. Subsequently, the HfO2 dielectric was deposited by evaporating hafnium in the presence of atomic oxygen. An in situ TaN metal gate was similarly deposited. Long channel devices were fabricated using a standard process flow. These devices exhibited a low equivalent oxide thickness (EOT) of 0.7nm with gate leakage less than 15mA∕cm2 at VFB+1V. Device mobility was extracted from Is-Vg and split C-V characteristics. Results indicate a 2× mobility enhancement in Ge p-MOSFET devices compared to Si control devices. The demonstration of subnanometer EOT suggests that high-k gate dielectrics on ger...

Atomic layer deposition of insulating nitride interfacial layers for germanium metal oxide semiconductor field effect transistors with high-κ-oxide/tungsten nitride gate stacks

Atomic layer deposition (ALD) was used to deposit passivating interfacial nitride layers between Ge and high-κ oxides. High-κ oxides on Ge surfaces passivated by ultrathin (1–2nm) ALD Hf3N4 or AlN layers exhibited well-behaved C-V characteristics with an equivalent oxide thickness as low as 0.8nm, no significant flatband voltage shifts, and midgap density of interface states values of 2×1012cm−1eV−1. Functional n-channel and p-channel Ge field effect transistors with nitride interlayer/high-κ oxide/metal gate stacks are demonstrated.

Ge n-MOSFETs on lightly doped substrates with high-/spl kappa/ dielectric and TaN gate

In this letter, we report successful fabrication of germanium n-MOSFETs on lightly doped Ge substrates with a thin HfO/sub 2/ dielectric (equivalent oxide thickness /spl sim/10.8 /spl Aring/) and TaN gate electrode. The highest peak mobility (330 cm/sup 2//V/spl middot/s) and saturated drive current (130 /spl mu/A/sq at V/sub g/--V/sub t/=1.5 V) have been demonstrated for n-channel bulk Ge MOSFETs with an ultrathin dielectric. As compared to Si control devices, 2.5/spl times/ enhancement of peak mobility has been achieved. The poor performance of Ge n-MOSFET devices reported recently and its mechanism have been investigated. Impurity induced structural defects are believed to be responsible for the severe degradation.

Investigation of Carrier Transport in Germanium MOSFETs With

To improve source injection velocity and consequently MOSFET performance, high mobility semiconductors are being explored as possible replacements for silicon. Germanium offers enhanced electron mobility and superior hole mobility at high inversion charge density; however, formation of a high quality germanium-dielectric interface remains a serious challenge. High-K dielectrics deposited directly on germanium exhibit poor physical and electrical properties, so an interfacial layer is required. Proposed interlayers include GeON, Si, and metal nitrides such as AlN and Hf3N4. To date, reported electron mobilities have been disappointing. In this letter, carrier transport in Ge MOSFETs with WN/AI2O3AIN gate stacks is investigated using surface-channel and buried-channel devices. Peak mobilities of 300 and 600 cm2/ V ldr s are observed for buried-channel p- and n-FETs, respectively. Evidence of phosphorus passivation of the germanium-dielectric interface is also presented.

\hbox{WN}/\hbox{Al}_{2}\hbox{O}_{3}/\hbox{AlN}

An in situ surface-cleaning technique by annealing germanium substrates at 550 degC in Ar gas is investigated. Reduced equivalent oxide thickness confirms the effective removal of native oxides by this technique. Improved electrical characteristics in terms of reduced interface-state density and slow trap density are demonstrated in the Ge MOS devices, with surface-nitridation treatment and chemical vapor deposited HfO2 high-kappa dielectric, suggesting the advantage of this technique. Significant elimination of GeOxN y interfacial layer is observed from cross-sectional transmission electron microscopy images after 600 degC postmetallization anneal, suggesting that an interface passivation technique having better thermal stability is required in order to suppress the severe interdiffusion across the interface between Ge substrate and the upper dielectric layer