Weiping Bai

Theoretical and experimental investigation of Si nanocrystal memory device with HfO/sub 2/ high-k tunneling dielectric

This paper describes improved memory characteristics of the Si nanocrystal memory devices by replacing the traditional SiO/sub 2/ with HfO/sub 2/ high-k dielectrics for the first time. Thanks to the combination of a lower electron barrier height and a larger physical thickness of HfO/sub 2/ as compared with SiO/sub 2/, the fabricated device shows excellent programming efficiency and data retention characteristic. The single-electron charging effect is clearly observed at room temperature. It also shows superior data endurance up to 10/sup 6/ write/erase cycles.

Ge diffusion in Ge metal oxide semiconductor with chemical vapor deposition HfO2 dielectric

We report a study on Ge diffusion and its impact on the electrical properties of TaN∕HfO2∕Ge metal-oxide-semiconductor (MOS) device. It is found that Ge diffusion depends on the amount of GeO2 formed at the HfO2∕Ge interface and can be retarded by surface nitridation. It is speculated that Ge diffusion is in the form of GeO or Ge-riched HfGeO. Effective suppression of Ge diffusion by NH3 nitridation has resulted in improved electrical properties of TaN∕HfO2∕Ge MOS device, including equivalent oxide thickness (EOT), leakage current, hysteresis, and interface state density. The degradation of leakage current after high temperature post metallization anneal (PMA) is found to be due to Ge diffusion.

A novel MONOS-type nonvolatile memory using high-/spl kappa/ dielectrics for improved data retention and programming speed

This paper presents a novel metal-oxide-nitride-oxide-silicon (MONOS)-type nonvolatile memory structure using hafnium oxide (HfO/sub 2/) as tunneling and blocking layer and tantalum pentoxide (Ta/sub 2/O/sub 5/) as the charge trapping layer. The superiorities of such devices to traditional SiO/sub 2/-Si/sub 3/N/sub 4/-SiO/sub 2/ stack devices in obtaining a better tradeoff between faster programming and better retention are illustrated based on a band engineering analysis. The experimental results demonstrate that the fabricated devices can be programmed as fast as 1 /spl mu/s and erased from 10 ns at an 8-V gate bias. The retention decay rate of this device is improved by a factor more than three as compared to the conventional MONOS/SONOS type devices. Excellent endurance and read disturb performance are also demonstrated.

Epitaxial strained germanium p-MOSFETs with HfO/sub 2/ gate dielectric and TaN gate electrode

Germanium p-MOSFETs with a thin high-k dielectric (EOT/spl sim/1.6 nm) were fabricated on bulk Ge and epitaxial germanium-on-silicon substrates. These devices exhibited sub-90 mV/decade subthreshold swing and low gate leakage. The IV and CV characteristics achieved in this work allow for accurate extraction of important device parameters such as transconductance (Gm) and low-field mobility. Results from n-MOSFETs fabricated on bulk Ge substrates are also presented.

Ge n-MOSFETs on lightly doped substrates with high-/spl kappa/ dielectric and TaN gate

In this letter, we report successful fabrication of germanium n-MOSFETs on lightly doped Ge substrates with a thin HfO/sub 2/ dielectric (equivalent oxide thickness /spl sim/10.8 /spl Aring/) and TaN gate electrode. The highest peak mobility (330 cm/sup 2//V/spl middot/s) and saturated drive current (130 /spl mu/A/sq at V/sub g/--V/sub t/=1.5 V) have been demonstrated for n-channel bulk Ge MOSFETs with an ultrathin dielectric. As compared to Si control devices, 2.5/spl times/ enhancement of peak mobility has been achieved. The poor performance of Ge n-MOSFET devices reported recently and its mechanism have been investigated. Impurity induced structural defects are believed to be responsible for the severe degradation.

High quality ultra thin CVD HfO/sub 2/ gate stack with poly-Si gate electrode

We have developed and demonstrated an in-situ rapid thermal CVD (RTCVD) process for the fabrication of high quality ultra thin CVD HfO/sub 2/ gate stack that is compatible with conventional self-aligned poly-Si gate technology. These poly-Si gated HfO/sub 2/ gate stack show excellent interface properties, EOT=10.4 /spl Aring/, and leakage current Jg=0.23 mA/cm/sup 2/ @Vg=-1 V which is several orders of magnitude lower than RTO SiO/sub 2/ with poly-Si gate. In addition, the HfO/sub 2/ gate stack is thermally stable in direct contact with n/sup +/-poly Si gate under typical dopant activation conditions. These films also show excellent reliability under high-field electrical stress. We have also fabricated and demonstrated NMOSFETs, and studied boron penetration in HfO/sub 2/ gate stack with p/sup +/-poly Si gate.

MOS characteristics of ultra thin rapid thermal CVD ZrO/sub 2/ and Zr silicate gate dielectrics

In this paper, we report MOS characteristics of ultra thin, high quality CVD ZrO/sub 2/ and Zr silicate (Zr/sub 27/Si/sub 10/O/sub 63/) gate dielectrics deposited on Si substrates by in-situ rapid thermal processing. These high-K gate dielectrics show excellent equivalent oxide thickness (EOT) of 8.9 /spl Aring/ (ZrO/sub 2/) and 9.6 /spl Aring/ (Zr/sub 27/Si/sub 10/O/sub 63/) with extremely low leakage current of 20 mA/cm/sup 2/ and 23 mA/cm/sup 2/ @Vg=-1 V, respectively. The thermal stability of ZrO/sub 2//Si as well as the poly-Si/ZrO/sub 2/ interfaces are examined using in-situ XPS. We also investigate the conduction mechanisms and long-term reliability in these gate stacks. In addition, the effects of various gate electrode materials (Al/TiN, poly-SiGe, and poly-Si) on the electrical properties of gate stacks are studied. Finally, we also study the boron diffusion behaviors in p/sup +/-poly-Si PMOS.

Three-Layer laminated metal gate electrodes with tunable work functions for CMOS applications

This letter presents a novel technique for tuning the work function of a metal gate electrode. Laminated metal gate electrodes consisting of three ultrathin (/spl sim/1-nm) layers, with metal nitrides (HfN, TiN, or TaN) as the bottom and top layers and element metals (Hf, Ti, or Ta) as the middle layer, were sequentially deposited on SiO/sub 2/, followed by rapid thermal annealing annealing. Annealing of the laminated metal gate stacks at high temperatures (800/spl deg/C-1000/spl deg/C) drastically increased their work functions (as much as 1 eV for HfN-Ti-TaN at 1000/spl deg/C). On the contrary, the bulk metal gate electrodes (HfN, TiN and TaN) exhibited consistent midgap work functions with only slight variation under identical annealing conditions. The work function change of the laminated metal electrodes is attributed to the crystallization and the grain boundary effect of the laminated structures after annealing. This change is stable and not affected by subsequent high-temperature process. The three-layer laminated metal gate technique provides PMOS-compatible work functions and excellent thermal stability even after annealing at 1000/spl deg/C.

High quality CVD TaN gate electrode for sub-100 nm MOS devices

In this paper, for the first time, we present a detailed evaluation of physical and electrical properties of CVD TaN as a potential gate electrode material for sub-100 nm MOS device applications. Our results show that CVD TaN films deposited using TBTDET (tertbutylimidoirisdiethylamido tantalum) exhibit excellent thermal stability with underlying ultra thin SiO/sub 2/ up to 1000/spl deg/C and extremely stable work function (5eV@800-1000/spl deg/C) suitable for p-MOS device applications. Compared to PVD TaN, MOS devices with CVD TaN gate electrode show desirable work function for p-MOS devices, excellent stability of gate oxide thickness, leakage current, and interface properties during high-temperature annealing, and superior gate dielectric TDDB reliability. These results suggest that CVD TaN can be used as the gate electrode on ultra thin gate oxide in self-aligned gate-first CMOS processing.

Molybdenum metal gate MOS technology for post-SiO/sub 2/ gate dielectrics

Mo metal gate p-MOSFETs with several advanced gate dielectrics were fabricated. A suitable p-MOSFET work function was achieved and good device characteristics were obtained in all cases. Thermodynamic stability of Mo on Si/sub 3/N/sub 4/, ZrO/sub 2/ and ZrSiO/sub 4/ was verified by good carrier mobility agreement with the universal mobility model.