A. Souifi

Electrical study of Ge-nanocrystal-based metal-oxide-semiconductor structures for p-type nonvolatile memory applications

Nonvolatile memory structures using Ge nanocrystals embedded in SiO2 have been characterized by room and low temperature current–voltage and capacitance–voltage measurements. The Ge nanocrystals have been fabricated by low pressure chemical vapor deposition process which is shown to be well suited for a real control of the tunnel oxide thickness. The deposition conditions allow a separate control of nc-Ge density and size. Using capacitance–voltage characterizations on nonvolatile memory structures, we have measured the charging and discharging kinetics of holes for tunnel oxides in the range 1.2–2.5 nm. Using current–voltage measurements and simulations, we have also shown that nc-Ge are at the origin of a tunnel-assisted current. Simulations have demonstrated that the hole’s charging effects strongly reduce the current density across the nonvolatile memory structure. Combined with a good control of nc-Ge properties, the use of Ge dots with large diameters (>10 nm) seems to be a promising way for p-type ...

Lateral confinement by low pressure chemical vapor deposition-based selective epitaxial growth of Si1−xGex/Si nanostructures

Among the growth approaches being considered currently to realize quantum dots and quantum wires is the selective epitaxial growth on patterned substrates. With this technique the feature size and geometry are mainly limited by the lithographic process. With optical lithography we achieved a lateral dimension of ⩾0.4 μm. Therefore, to further reduce the lateral dimension, but still using optical lithography, the tendency toward facet formation during selective epitaxial growth was investigated. Si0.70Ge0.30 multiple quantum well structures with Si0.935Ge0.065 spacers and buffers were deposited on (001) Si. The buffer thickness was varied so as to achieve facet junction. While on large areas the Si0.935Ge0.065 buffer was relaxed, for dots ⩽300 μm or narrower the structures remained strained even for buffer thicknesses exceeding by a factor of two–three the critical thickness of large area. In dots and wires where facet junctioning has taken place a rounded region between facets (approximately 50 nm broad) ...

Nucleation control of CVD growth silicon nanocrystals for quantum devices

Abstract We present a study of nucleation and organization of Si quantum dots (Si QDs) grown on insulating layers. The samples were investigated by scanning electron microscopy, high-resolution transmission electron microscopy, and scanning tunneling microscope (STM). We demonstrate that the chemical nature of the surface influences the Si QDs nucleation. We have organized the Si QDs using a buried array of dislocations obtained by molecular bonding of Si wafers. The electrical properties of individual Si QDs were investigated and memory effects were shown in C-MOS transistors integrating Si QDs within the gate oxide.

Low pressure chemical vapor deposition growth of silicon quantum dots on insulator for nanoelectronics devices

Abstract We present a comparative study of nucleation and growth of Si quantum dots on SiO2, SiOxNy and Si3N4 substrates using silane low pressure chemical vapor deposition (LPCVD) at low temperature (570–610°C). The samples are investigated by atomic force micoscopy (AFM), scanning electron microscopy (SEM), high resolution transmission electron microscopy (HRTEM) and spectroscopic ellipsometry (SE). We show that the chemical nature of the surface, precisely, the presence of SiO bonds, decreases the Si quantum dot density. By optimising the deposition parameters, a Si dot density of 1012 cm−2 can be obtained below 600°C on a pure Si3N4 surface. The influence of hydrogen, provided by silane decomposition, on the Si nucleation mechanism will be discussed.

Novel integration process and performances analysis of Low STandby Power (LSTP) 3D multi-channel CMOSFET (MCFET) on SOI with metal / high-K gate stack

For the first time, ultra low I_OFF (16.5 pA/mum) and high I_ONN,P (2.27 mA/mum and 1.32 mA/mum) currents are obtained with a multi-channel CMOSFET (MCFET) architecture on SOI with a metal/high-K gate stack. This leads to the best I_ON/I_OFF ratios ever reported: 1.4 times 10⁸ (0.8 times 10⁸) for 50 nm n- (p-) MCFETs. We show, based on specifically developed integration process, characterization methods and analytical modeling, how those performances are obtained thanks to specific 3D MCFET features, in particular, transport properties, saturation regime and electrostatic behavior.

Photoluminescence and electrical characterization of SiGe/Si heterostructures grown by rapid thermal chemical vapour deposition

Abstract A systematic photoluminescence (PL) spectroscopy study on fully strained and partially relaxed SiGe layers grown on silicon by rapid thermal chemical vapour deposition (RTCVD) is reported. The recent observation in fully strained SiGe single layers of a well-resolved excitonic luminescence transition consisting of a no-phonon line followed by phonon-mode replicas is accurately analysed and is interpreted as a free excitonic transition subject to localization by a fluctuating random alloy potential. The clear observation of such a PL excitonic transition with a measured lifetime of 9 μs shows that our thin strained SiGe layers grown by RTCVD exhibit high quality electronic properties. This corresponds to a low residual impurity content, freedom from crystal defects and low concentration of non-radiative band gap deep levels. We point out in this study the usefulness of this excitonic transition measurement for accessing directly and with accuracy the fundamental optical band gap energy of the tetragonally distorted strained SiGe material, and for probing alloy fluctuation in the layer and at the hetero-interface. The relaxation process which can occur when the thickness increases has been investigated by measuring the change in the PL features. This work shows that, when the PL excitonic transition vanishes, defect-related deep PL bands assumed to be assigned to the presence of dislocations in the SiGe layer begin to appear. These defect-related deep PL bands are tentatively connected to deep levels observed by transient capacitance spectroscopy in the SiGe layer and at the hetero-interface.

New aspects and mechanism of kink effect in InAlAs/InGaAs/InP inverted HFETs

The kink effect in InAlAs/InGaAs/InP composite channel heterojunction field effect transistors (HFETs) was investigated as a function of temperature and optical excitation. Drain source and gate current measurements show that above 325 K the kink effect disappears while the impact ionization process is still present. The kink at low temperatures is suppressed by illumination with photons of energy above 1 eV. These results prove that this parasitic effect is mainly related to the presence of traps in the top layers.

Electrical and optical characterisation of vanadium in 4H and 6H–SiC

Abstract Vanadium deep acceptor level in bulk 6H–SiC and 4H–SiC has been studied by deep level transient spectroscopy (DLTS), optical absorption (OA), photoluminescence (PL) and deep level optical spectroscopy (DLOS). DLTS reveals two levels related to vanadium acceptor level (V3+/V4+) for 6H–SiC at Ec −0.68 eV (cubic sites) and Ec −0.74 eV (hexagonal site) and for 4H–SiC at Ec −0.82 eV. The good correlation obtained between DLOS and OA spectra allows us to identify OA lines and DLOS resonance band as V3+ internal transition between the 3A2 ground state towards excited states. The V3+ ion configuration in 4H–SiC is given.

Retention in metal-oxide-semiconductor structures with two embedded self-aligned Ge-nanocrystal layers

Structural and electrical characterization has been carried out on metal–oxide–semiconductor (MOS) structures with a silicon dioxide (SiO2) layer containing a germanium nanocrystals (Ge-ncs) floating gate. Ge-nc layers were embedded in SiO2 by ion implantation with subsequent annealing. Structural analysis proved the presence of two self-aligned nanocrystal layers within the SiO2 host material. The electrical results indicate a strong memory effect due to the presence of a near-interface Ge-nc layer. Few volts memory windows can easily be obtained at relatively low programming voltages (<6 V). For comparison, operating voltages used in current FLASH technology are about 12 V. Despite its promising structural properties, retention times extracted from capacitance measurements and scanning Kelvin microscopy were found to be too low (~105 s) to comply with the non-volatility industry requirements (<10 years required).

Traps centers and deep defects contribution in current instabilities for AlGaN/GaN HEMT's on silicon and sapphire substrates

Abstract AlGaN/GaN high electron mobility transistors (HEMTs) with Si and Al 2 O 3 substrates reveals anomalies on I ds – V ds – T and I gs – V gs – T characteristics (degradation in drain current, kink effect, barrier height fluctuations, etc.). Stress and random telegraph signal (RTS) measurements prove the presence of trap centers responsible for drain current degradation. An explanation of the trapping mechanism responsible for current instabilities is proposed. Deep defects analysis performed by capacitance transient spectroscopy ( C -DLTS), frequency dispersion of the output conductance ( G ds ( f )), respectively, on gate/source and drain/source contacts and RTS prove the presence of deep defects localized, respectively, in the gate and in the channel regions. Defects detected by C -DLTS and G ds ( f ) are strongly correlated, respectively, to barrier height inhomogeneities and kink anomalies. Gate current analysis confirms the presence of ( G – R ) centers acting like traps at the interface GaN/AlGaN. Finally, the localization of these traps defects is proposed.