A'zraa Afhzan Ab Rahim

Low power CMOS charge sharing dynamic latch comparator using 0.18μm technology

This paper discusses the design and analysis of a latching comparator using charge sharing circuit topology for low power and high speed. This topology combines the good features of the resistive dividing comparator and the differential current sensing comparator. This design will be focusing on the minimization of propagation delay and the power dissipation of the comparator, which will improves the comparator performance. Simulation results have been obtained using 0.18μm technology, for a 100 MHz clocked comparator, considering 1.8V supply voltage and 1.8V input range. Design has been carried out in SILVACO EDA tool, the schematic simulations are using Gateway SILVACO EDA tool and layout simulations are verified using Expert SILVACO EDA tool.

Comparative study on CMOS SRAM sense amplifiers using 90nm technology

This paper will investigate the sensing delay optimization and power consumption of each sense amplifier. The optimization will apply multi-Vth or MTCMOS techniques for better sensing delay, with the critical path transistors will use low-Vth model. The initial optimization is done by calculating for the most proper transistor sizing in term of sensing delay and power. The result obtained shows MTCMOS design improves sensing delay in term of smaller bit-lines difference (ΔBL) required for full-swing amplification as compared to single std-Vth. MTCMOS design also improves total power consumption at least 12% reduction as compared to single std-Vth design. The selected sense amplifier circuits to be simulated are Current Sense Amplifier (CSA), Charge-Transfer Sense Amplifier (CTSA), and High-Speed Sense Amplifier (HSSA). The SRAM used is basic 6T SRAM for general purpose only.

Classification of watermelon leaf diseases using neural network analysis

This paper mainly discussed the process to classify Anthracnose and Downey Mildew, watermelon leaf diseases using neural network analysis. A few of infected leaf samples were collected and they were captured using a digital camera with specific calibration procedure under controlled environment. The classification on the watermelons leaf diseases is based on color feature extraction from RGB color model where the RGB pixel color indices have been extracted from the identified Regions of Interest (ROI). The proposed automated classification model involved the process of diseases classification using Statistical Package for the Social Sciences (SPSS) and Neural Network Pattern Recognition Toolbox in MATLAB. Determinations in this work have shown that the type of leaf diseases achieved 75.9% of accuracy based on its RGB mean color component.

Multi-sized Output Cache Controllers

This project describes the design of a Multi-sized Output Cache Controller that will handle 2Kbyte 16 ways with 4 word block size cache. A cache controller is a device that used to sequence the read and write of the cache storage array. Most of modern microprocessor is designed with multiple core architecture that will lead to massive traffic of cache data transfer. By taking the advantage of using temporal locality and spatial locality to the cache, the problem can be solved. With this solution, a controller that capable to handle huge amount of way and block size need to be designed. This design will be implemented using Xilinx software. It was developed base on Verilog coding. Using the same software, a test bench was constructed to test the functionality of the controller. This cache controller consists of four stages, from request to read data. It had the capability to read and write to different agent on various output data size from 1byte till 16 byte.

Comparative study of comparator and encoder in a 4-bit Flash ADC using 0.18μm CMOS technology

This paper describes a comparative study of comparator and encoder in 4-bit Flash Analog to Digital Converter (ADC) for Pipeline ADC to obtain a high speed ADC. In this paper, the conventional comparator is replaced with an open loop comparator and the non-ROM type encoder is used as the alternative for the conventional encoder. It is implemented using 0.18μm CMOS technology. Generally, the Silvaco Electronic Design Automation (EDA) tools is used for drawing the schematics, do the simulations and designing the layout of the proposed Flash ADC. The simulation results include 1.8V analog input range and 24.2662 mW of power dissipation at maximum sampling frequency of 500MHz with the lowest propagation delay time of 539.61ps.

A Non-invasive Method to Measure the Sweetness of Malaysian Papaya Quantitatively Using NIR Full-transmittance Technique - A Preliminary Study

The fruit industry requires rapid, economical, and non destructive method for classifying fruits by internal quality. This research studied the development of a non destructive method that would enable consumers and producers to assess the maturity of papayas rapidly. Near Infra Red Spectroscopy (NIRS) was used to assess total Soluble Solid Content (SSC). A device consisting of infrared receiver sensor was developed to receive the infrared wavelength and a circuit was constructed to convert this reading into voltage. Fuzzy logic was applied as a decision support system to classify the sweetness of Malaysian papayas. The selected papayas were classified with two different categories which was ripe and unripe. Evaluation from the developed FIS scheme was compared with the results obtained from the refractometer which is in term of %Brix. It was found that the voltage obtained is proportional to the % Brix.

Programmable Logic Controller (PLC) for polymer mixing tank

This project focuses on improving the performance of a plants sludge dewatering process by using Omron CP1E Programmable Logic Controller (PLC) to increase the efficiency of the process which leads to a reduction in cost of the polymer product. The process requires manually mixing the cationic polymer long chains with raw water to produce a product that will be sent to the sludge tank process and filter press process where the sludge will harden for disposal. The addition of PLC into the process will reduce error caused by human. The Omron PLC will control the water intake inlet and pump for polymer needed to be mixed by measuring the level of water inside the tank using the sensor to control amount of water and polymer. The project works on upgrading an established system that uses manual mix method to automated method that will produce more accurate concentration of polymer without any human error.

Comparative study on multistage amplifier and folded cascode amplifier design in sample and hold circuit using 0.18μm CMOS technology

This paper presents the comparison between multistage amplifier and folded cascode amplifier design using 0.18μm CMOS technology. The objective of this project is to compare gain and power dissipation between these two design models. Sample and hold circuit (SHC) is the main component in pipelined ADC. Designing a low power, high gain SHC is crucial, that is the main reason why multistage amplifier is applied in this project. Implementation has been done in 0.18μm technology, for a 5MHz sampling frequency, considering 1.2 Vpp voltage and 1.8V voltage supply using SILVACO EDA tools. From the simulation, the multistage amplifier consumes 0.139mW power and has gain of 94.64dB. The folded cascode amplifier has 6.5mW power dissipation and 70dB gain. From the simulation results, the multistage amplifier is better in term of gain and power dissipation than the folded cascode design.