Aaron Vallett

Experimental demonstration of 100nm channel length In 0.53 Ga 0.47 As-based vertical inter-band tunnel field effect transistors (TFETs) for ultra low-power logic and SRAM applications

Vertical In<inf>0.53</inf>Ga<inf>0.47</inf>As tunnel field effect transistors (TFETs) with 100nm channel length and high-k/metal gate stack are demonstrated with high I<inf>on</inf>/I<inf>off</inf> ratio (≫10⁴). At V<inf>DS</inf> = 0.75V, a record on-current of 20µA/µm is achieved due to higher tunneling rate in narrow tunnel gap In<inf>0.53</inf>Ga<inf>0.47</inf>As. The TFETs exhibit gate bias dependent NDR characteristics at room temperature under forward bias confirming band to band tunneling. The measured data are in excellent agreement with two-dimensional numerical simulation at all drain biases. A novel 6T TFET SRAM cell using virtual ground assist is demonstrated despite the asymmetric source/drain configuration of TFETs.

Fabrication and characterization of axially doped silicon nanowire tunnel field-effect transistors.

Tunnel field-effect transistors were fabricated from axially doped silicon nanowire p-n junctions grown via the vapor-liquid-solid method. Following dry thermal oxidation to form a gate dielectric shell, the nanowires have a p-n-n(+) doping profile with an abrupt n-n(+) junction, which was revealed by scanning capacitance microscopy. The lightly doped n-segment can be inverted to p(+) by modulating the top gate bias, thus forming an abrupt gated p(+)-n(+) junction. A band-to-band tunneling current flows through the electrostatically doped p(+)-n(+) junction when it is reverse biased. Current-voltage measurements performed from 375 down to 4.2 K show two different regimes of tunneling current at high and low temperatures, indicating that there are both direct band-to-band and trap-assisted tunneling paths.

Disorder dominated microwave conductance spectra of doped silicon nanowire arrays.

Conductance spectra of doped silicon nanowire (SiNW) arrays were measured from 0.5 to 50 GHz at temperatures between 4 and 293 K. For arrays consisting of 11 to >10(4) SiNWs, the conductance was found to increase with frequency as f(s), with 0.25 < s < 0.45, consistent with behavior found universally in disordered systems. A possible cause is disorder from Si/SiO x interface states dominating the conductance due to the high surface-to-volume ratio of the nanowires.

Fabrication of axially-doped silicon nanowire tunnel FETs and characterization of tunneling current

Recent interest in low-power electronics has sparked considerable interested in gate-controlled tunneling-based transistors (TFETs), which have demonstrated inverse subthreshold slopes (S) better than the MOSFET limit of 60 mV/dec.1 While the natural progression of these devices to nanoscale dimensions promises improved performance23, there is a lack of experimental data regarding the physics of tunneling at reduced dimensions. Here we present a TFET fabricated from an individual axially-doped p+-n-n+ Si nanowire in a device layout that enables the study of tunneling physics as the wire dimensions are scaled to the 1D transport regime.

Inter-band Tunnel Transistor Architecture using Narrow Gap Semiconductors

The inter-band tunnel transistor (TFET) architecture features a sub-kT/q sub-threshold slope operation and can potentially support high ION/IOFF ratios over small gate voltages. Based on two-dimensional numerical simulations, we investigate TFET in various material systems ranging from silicon to indium arsenide. TFET performance can be enhanced when heterojunctions are employed at the source side to enhance tunneling, nonequilibrium carrier population is maintained in the channel and one dimensional tunneling junction are incorporated. Mixed mode circuit simulations using TFETs highlight the impact of feed forward gate-to-drain capacitance in these devices during transient switching operation and reveal important differences with MOSFETs. Narrow gap semiconductors with low density of states are projected as viable candidates to implement TFET architecture in sustaining an aggressive supply voltage scaling roadmap for future digital logic applications

Axially-doped n + -p − -n + and p + -n − -p + silicon nanowires: vapor-liquid-solid growth and field effect transistor characterization

Engineering materials at the nanoscale by combining controlled nanomaterial synthesis and directed assembly methods offers the potential to create new electronic and optical devices with improved performance and functionality. Semiconductor nanowires have been of particular interest as a model system for studying new physical phenomena arising from their scaled geometries as well as for applications in high performance vertical transistors, thin film electronic, electro-optical, and sensing devices and circuits. However, the use of relatively immature nanowire growth, in-situ doping, and device integration processes have made it difficult to elucidate and compare the electrical transport properties across different device platforms (e.g., nanowire versus planar) and length scales. This talk will describe recent results showing that thermally-oxidized in-situ axially-doped n+-p--n+ and p+-n--p+ silicon nanowires (20 to 50 run in diameter) grown by the vapor-liquid-solid technique can be used to fabricate stable and reproducible n- and p-channel top-gate and wrap-around-gate field effect transistors (FETs) that operate by inversion ofthe channel and have both high on-state current (Ion) and on/off-state current ratio (Ion/Ioff). Control measurements using back-gated device structures that separately probe the properties of the heavily-doped source/drain regions and lightly-doped channel region confirm that radial thin film deposition on the channel is prevented during vapor-liquid-solid growth of the second heavily-doped nanowire segment, which is necessary for fabricating complementary field effect transistors using these silicon nanowires. The effective mobility estimated from the measured channel resistance of n+-p--n+ and p+-n--p+ silicon nanowire FETs having 1 ?m-long channels will be provided and related to planar devices. Finally, the properties of the top-gate and wrap-around-gate n- and p-channel silicon nanowire FETs will be compared as a function of global back gate bias.

Microwave Dissipation Spectra in Arrays of Silicon Nanowires

The transmission and reflection scattering parameters of arrays of silicon nanowires (SiNWs) directly assembled onto co-planar waveguides (CPWs) have been measured from 0.1 to 50 GHz at room temperature. Typical arrays consisted of between 103 to 104 SiNWs aligned parallel to the electric field polarization of the propagating microwave field. Scattering parameters were measured on CPWs both before and after nanomaterial assembly. Highly reproducible CPW characteristics and careful use of control samples to quantify systematic reproducibility allowed clear separation of nanomaterial effects from the characteristics of the bare CPWs. Arrays of n doped SiNWs consistently showed frequency-dependent power dissipation. Nominally undoped SiNW arrays, however, showed no measurable microwave power dissipation up to 50 GHz.

RF/Microwave properties and applications of directly assembled nanotubes and nanowires: LDRD project 102662 final report.

LDRD Project 102662 provided support to pursue experiments aimed at measuring the basic electrodynamic response and possible applications of carbon nanotubes and silicon nanowires at radiofrequency to microwave frequencies, approximately 0.01 to 50 GHz. Under this project, a method was developed to integrate these nanomaterials onto high-frequency compatible co-planar waveguides. The complex reflection and transmission coefficients of the nanomaterials was studied as a function of frequency. From these data, the high-frequency loss characteristics of the nanomaterials were deduced. These data are useful to predict frequency dependence and power dissipation characteristics in new rf/microwave devices incorporating new nanomaterials.